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| REJ09B0353-0300 The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 16 H8/3039 Group, H8/3039F-ZTATTM Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8 Family / H8/300H Series H8/3037 HD6433037F H8/3039 HD64F3039F HD6433037TE HD64F3039TE HD6433037VF HD64F3039VF HD6433037VTE HD64F3039VTE H8/3036 HD6433036F HD6433039F HD6433036TE HD6433039TE HD6433036VF HD6433039VF HD6433036VTE HD6433039VTE H8/3038 HD6433038F HD6433038TE HD6433038VF HD6433038VTE Rev.3.00 Revision date: Mar. 26, 2007 www.renesas.com Notes regarding these materials 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries. Rev.3.00 Mar. 26, 2007 Page ii of xxii REJ09B0353-0300 General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions may occur due to the false recognition of the pin state as an input signal. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products. Rev.3.00 Mar. 26, 2007 Page iii of xxii REJ09B0353-0300 Rev.3.00 Mar. 26, 2007 Page iv of xxii REJ09B0353-0300 Preface The H8/3039 Group comprises high-performance single-chip microcomputers (MCUs) that integrate system supporting functions together with an H8/300H CPU core. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, I/O ports, and other facilities. Of the two SCI channels, one has been expanded to support the ISO/IEC 7816-3 smart card interface. Functions have also been added to reduce power consumption in battery-powered applications: individual modules can be placed in standby, and the frequency of the system clock supplied to the chip can be divided down under software control. The five MCU operating modes offer a choice of expanded mode, single-chip mode, and address space size, enabling the H8/3039 Group to adapt quickly and flexibly to a variety of conditions. In addition to its mask-ROM versions, the H8/3039 Group has an F-ZTATTM version with user programmable on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications. This manual describes the H8/3039 Group hardware. For details of the instruction set, refer to the H8/300H Series Software Manual. Note: F-ZTAT is a trademark of Renesas Technology Corp. Rev.3.00 Mar. 26, 2007 Page v of xxii REJ09B0353-0300 Rev.3.00 Mar. 26, 2007 Page vi of xxii REJ09B0353-0300 Main Revisions for This Edition Item All Page -- Revision (See Manual for Details) * * 2.3 Address Space Figure 2.2 Memory Map 20 Notification of change in company name amended (Before) Hitachi, Ltd. (After) Renesas Technology Corp. Product naming convention amended (Before) H8/3039 Series (After) H8/3039 Group Figure amended H'0000 H'FFFF 1. Normal mode (64-Kbyte mode) 5.2.2 Interrupt Priority 91 Registers A and B (IPRA, IPRB) Interrupt Priority Register B (IPRB) 5.2.3 IRQ Status Register (ISR) 93 Description amended Bit Initial value Read/Write 7 IPRB7 0 R/W 6 IPRB6 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 IPRB3 0 R/W 2 IPRB2 0 R/W 1 IPRB1 0 R/W 0 -- 0 R/W Description amended Bits 5, 4, 1 and 0--IRQ5, IRQ4, IRQ1 and IRQ0 Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F): These bits indicate the status of IRQ5, IRQ4, IRQ1, and IRQ0 interrupt requests. 5.2.4 IRQ Enable Register (IER) 94 Description amended Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W Reserved bits Bits 5, 4, 1, and 0--IRQ5, IRQ4, IRQ1, and IRQ0 Enable (IRQ5E, IRQ4E, IRQ1E, IRQ0E): These bits enable or disable IRQ5 , IRQ4 , IRQ1 , IRQ0 interrupts. Rev.3.00 Mar. 26, 2007 Page vii of xxii REJ09B0353-0300 Item 5.3.3 Interrupt Vector Table Table 5.3 Interrupt Sources, Vector Addresses, and Priority 5.5.4 Usage Notes Figure 5.9 IRQnF Flag when Interrupt Exception Handling is not Executed Page 98 Revision (See Manual for Details) Table amended WOVI (interval timer) 109 Figure amended 1 read 0 written 1 read 0 written (Inadvertent clearing) Generation condition (2) 6.4.2 Precautions on Setting ASTCR and ABWCR* 131 Description amended Modes 5 and 7 ASTCR0 = 0 ABWCR = H'FC 11.2.8 Bit Rate Register (BRR) Table 11.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode 349 Description added The baud rate generator is controlled separately for the individual channels, so different values may be set for each. 351 Table amended (MHz) 12 Bit Rate (bits/s) 300 n 2 N 77 Error (%) 0.16 11.3.4 Synchronous Operation Clock 376 Description amended An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 and CKE0 bits in SCR and the C/A bit in SMR. See table 11.9. Rev.3.00 Mar. 26, 2007 Page viii of xxii REJ09B0353-0300 Item 16.2.1 Connecting a Crystal Resonator Table 16.2 Crystal Resonator Parameters 18.1.3 AC Characteristics Table 18.5 Control Signal Timing Page 500 Revision (See Manual for Details) Preliminary deleted 532 Table amended Condition A 8 MHz Item RES setup time RES pulse width Symbol tRESS tRESW Min 200 10 200 Max -- -- -- Condition B 10 MHz Min 200 10 200 Max -- -- -- Min 200 10 200 Condition C 18 MHz Max -- -- -- Unit ns tcyc ns Test Conditions Figure 18.10 Mode programming tMDS setup time (MD0, MD1, MD2) 18.1.4 A/D Conversion 535 Characteristics 18.2.2 DC Characteristics Table 18.10 Permissible Output Currents A.1 Instruction List 8. Block transfer instructions 576 541 Newly added Table amended Item Permissible output low current (total) Total of 27 pins including ports 1, 2, 5 and B Table amended Mnemonic EEPMOV. W Operand Size Operation -- if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next A.3 Number of States 584 Required for Execution Table A.4 Number of Cycles per Instruction Table amended Word Data Access M Normal Advanced Internal Operation N 2 2 Instruction BSR Mnemonic BSR d:16 Rev.3.00 Mar. 26, 2007 Page ix of xxii REJ09B0353-0300 All trademarks and registered trademarks are the property of their respective owners. Rev.3.00 Mar. 26, 2007 Page x of xxii REJ09B0353-0300 Contents Section 1 Overview............................................................................................................. 1.1 1.2 1.3 Overview........................................................................................................................... Block Diagram .................................................................................................................. Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions ....................................................................................................... Pin Functions .................................................................................................................... 1 1 6 7 7 8 12 1.4 Section 2 CPU ...................................................................................................................... 17 2.1 Overview........................................................................................................................... 2.1.1 Features................................................................................................................ 2.1.2 Differences from H8/300 CPU............................................................................. CPU Operating Modes ...................................................................................................... Address Space ................................................................................................................... Register Configuration ...................................................................................................... 2.4.1 Overview.............................................................................................................. 2.4.2 General Registers ................................................................................................. 2.4.3 Control Registers ................................................................................................. 2.4.4 Initial CPU Register Values ................................................................................. Data Formats ..................................................................................................................... 2.5.1 General Register Data Formats ............................................................................ 2.5.2 Memory Data Formats ......................................................................................... Instruction Set ................................................................................................................... 2.6.1 Instruction Set Overview ..................................................................................... 2.6.2 Instructions and Addressing Modes ..................................................................... 2.6.3 Tables of Instructions Classified by Function...................................................... 2.6.4 Basic Instruction Formats .................................................................................... 2.6.5 Notes on Use of Bit Manipulation Instructions.................................................... Addressing Modes and Effective Address Calculation ..................................................... 2.7.1 Addressing Modes ............................................................................................... 2.7.2 Effective Address Calculation ............................................................................. Processing States............................................................................................................... 2.8.1 Overview.............................................................................................................. 2.8.2 Program Execution State...................................................................................... 2.8.3 Exception-Handling State .................................................................................... 2.8.4 Exception-Handling Sequences ........................................................................... 2.8.5 Reset State............................................................................................................ 17 17 18 19 20 21 21 22 23 24 25 25 27 28 28 29 31 40 41 41 41 45 49 49 49 50 51 53 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Rev.3.00 Mar. 26, 2007 Page xi of xxii REJ09B0353-0300 2.9 2.8.6 Power-Down State ............................................................................................... Basic Operational Timing ................................................................................................. 2.9.1 Overview.............................................................................................................. 2.9.2 On-Chip Memory Access Timing........................................................................ 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 2.9.4 Access to External Address Space ....................................................................... 53 54 54 54 55 56 Section 3 MCU Operating Modes .................................................................................. 57 3.1 Overview........................................................................................................................... 3.1.1 Operating Mode Selection ................................................................................... 3.1.2 Register Configuration......................................................................................... Mode Control Register (MDCR) ...................................................................................... System Control Register (SYSCR) ................................................................................... Operating Mode Descriptions ........................................................................................... 3.4.1 Mode 1 ................................................................................................................. 3.4.2 Mode 3 ................................................................................................................. 3.4.3 Mode 5 ................................................................................................................. 3.4.4 Mode 6 ................................................................................................................. 3.4.5 Mode 7 ................................................................................................................. Pin Functions in Each Operating Mode ............................................................................ Memory Map in Each Operating Mode ............................................................................ Restrictions on Use of Mode 6.......................................................................................... 57 57 58 59 60 62 62 62 62 62 62 63 63 72 3.2 3.3 3.4 3.5 3.6 3.7 Section 4 Exception Handling ......................................................................................... 75 4.1 Overview........................................................................................................................... 4.1.1 Exception Handling Types and Priority............................................................... 4.1.2 Exception Handling Operation ............................................................................ 4.1.3 Exception Vector Table ....................................................................................... Reset.................................................................................................................................. 4.2.1 Overview.............................................................................................................. 4.2.2 Reset Sequence .................................................................................................... 4.2.3 Interrupts after Reset............................................................................................ Interrupts........................................................................................................................... Trap Instruction................................................................................................................. Stack Status after Exception Handling.............................................................................. Notes on Stack Usage ....................................................................................................... 75 75 75 76 78 78 78 80 80 81 81 82 4.2 4.3 4.4 4.5 4.6 Section 5 Interrupt Controller .......................................................................................... 83 5.1 Overview........................................................................................................................... 83 5.1.1 Features................................................................................................................ 83 5.1.2 Block Diagram..................................................................................................... 84 Rev.3.00 Mar. 26, 2007 Page xii of xxii REJ09B0353-0300 5.2 5.3 5.4 5.5 5.1.3 Pin Configuration................................................................................................. 5.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 5.2.1 System Control Register (SYSCR) ...................................................................... 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) ............................................. 5.2.3 IRQ Status Register (ISR).................................................................................... 5.2.4 IRQ Enable Register (IER) .................................................................................. 5.2.5 IRQ Sense Control Register (ISCR) .................................................................... Interrupt Sources ............................................................................................................... 5.3.1 External Interrupts ............................................................................................... 5.3.2 Internal Interrupts................................................................................................. 5.3.3 Interrupt Vector Table.......................................................................................... Interrupt Operation............................................................................................................ 5.4.1 Interrupt Handling Process................................................................................... 5.4.2 Interrupt Sequence ............................................................................................... 5.4.3 Interrupt Response Time...................................................................................... Usage Notes ...................................................................................................................... 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction ...................... 5.5.2 Instructions that Inhibit Interrupts........................................................................ 5.5.3 Interrupts during EEPMOV Instruction Execution .............................................. 5.5.4 Usage Notes ......................................................................................................... 85 85 86 86 88 93 94 95 96 96 97 97 100 100 105 106 107 107 108 108 108 Section 6 Bus Controller.................................................................................................... 111 6.1 Overview........................................................................................................................... 6.1.1 Features................................................................................................................ 6.1.2 Block Diagram ..................................................................................................... 6.1.3 Input/Output Pins ................................................................................................. 6.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 6.2.1 Access State Control Register (ASTCR) ............................................................. 6.2.2 Wait Control Register (WCR).............................................................................. 6.2.3 Wait State Controller Enable Register (WCER) .................................................. 6.2.4 Address Control Register (ADRCR).................................................................... Operation........................................................................................................................... 6.3.1 Area Division ....................................................................................................... 6.3.2 Bus Control Signal Timing .................................................................................. 6.3.3 Wait Modes.......................................................................................................... 6.3.4 Interconnections with Memory (Example) .......................................................... Usage Notes ...................................................................................................................... 6.4.1 Register Write Timing ......................................................................................... 6.4.2 Precautions on Setting ASTCR and ABWCR...................................................... 111 111 112 113 113 114 114 115 116 117 119 119 121 123 129 131 131 131 6.2 6.3 6.4 Rev.3.00 Mar. 26, 2007 Page xiii of xxii REJ09B0353-0300 Section 7 I/O Ports .............................................................................................................. 133 7.1 7.2 Overview........................................................................................................................... Port 1................................................................................................................................. 7.2.1 Overview.............................................................................................................. 7.2.2 Register Descriptions ........................................................................................... 7.2.3 Pin Functions in Each Mode ................................................................................ 7.3 Port 2................................................................................................................................. 7.3.1 Overview.............................................................................................................. 7.3.2 Register Descriptions ........................................................................................... 7.3.3 Pin Functions in Each Mode ................................................................................ 7.3.4 Input Pull-Up Transistors..................................................................................... 7.4 Port 3................................................................................................................................. 7.4.1 Overview.............................................................................................................. 7.4.2 Register Descriptions ........................................................................................... 7.4.3 Pin Functions in Each Mode ................................................................................ 7.5 Port 5................................................................................................................................. 7.5.1 Overview.............................................................................................................. 7.5.2 Register Descriptions ........................................................................................... 7.5.3 Pin Functions in Each Mode ................................................................................ 7.5.4 Input Pull-Up Transistors..................................................................................... 7.6 Port 6................................................................................................................................. 7.6.1 Overview.............................................................................................................. 7.6.2 Register Descriptions ........................................................................................... 7.6.3 Pin Functions in Each Mode ................................................................................ 7.7 Port 7................................................................................................................................. 7.7.1 Overview.............................................................................................................. 7.7.2 Register Description............................................................................................. 7.8 Port 8................................................................................................................................. 7.8.1 Overview.............................................................................................................. 7.8.2 Register Descriptions ........................................................................................... 7.8.3 Pin Functions ....................................................................................................... 7.9 Port 9................................................................................................................................. 7.9.1 Overview.............................................................................................................. 7.9.2 Register Descriptions ........................................................................................... 7.9.3 Pin Functions ....................................................................................................... 7.10 Port A................................................................................................................................ 7.10.1 Overview.............................................................................................................. 7.10.2 Register Descriptions ........................................................................................... 7.10.3 Pin Functions ....................................................................................................... 7.11 Port B ................................................................................................................................ 7.11.1 Overview.............................................................................................................. 133 137 137 138 140 142 142 143 145 147 148 148 148 150 152 152 153 155 156 157 157 158 160 163 163 163 164 164 165 167 168 168 168 170 172 172 173 175 182 182 Rev.3.00 Mar. 26, 2007 Page xiv of xxii REJ09B0353-0300 7.11.2 Register Descriptions ........................................................................................... 182 7.11.3 Pin Functions ....................................................................................................... 184 Section 8 16-Bit Integrated Timer Unit (ITU) ............................................................ 191 8.1 Overview........................................................................................................................... 8.1.1 Features................................................................................................................ 8.1.2 Block Diagrams ................................................................................................... 8.1.3 Input/Output Pins ................................................................................................. 8.1.4 Register Configuration......................................................................................... Register Descriptions ........................................................................................................ 8.2.1 Timer Start Register (TSTR)................................................................................ 8.2.2 Timer Synchro Register (TSNC) ......................................................................... 8.2.3 Timer Mode Register (TMDR) ............................................................................ 8.2.4 Timer Function Control Register (TFCR)............................................................ 8.2.5 Timer Output Master Enable Register (TOER) ................................................... 8.2.6 Timer Output Control Register (TOCR) .............................................................. 8.2.7 Timer Counters (TCNT) ...................................................................................... 8.2.8 General Registers (GRA, GRB) ........................................................................... 8.2.9 Buffer Registers (BRA, BRB).............................................................................. 8.2.10 Timer Control Registers (TCR) ........................................................................... 8.2.11 Timer I/O Control Register (TIOR) ..................................................................... 8.2.12 Timer Status Register (TSR)................................................................................ 8.2.13 Timer Interrupt Enable Register (TIER) .............................................................. CPU Interface.................................................................................................................... 8.3.1 16-Bit Accessible Registers ................................................................................. 8.3.2 8-Bit Accessible Registers ................................................................................... Operation........................................................................................................................... 8.4.1 Overview.............................................................................................................. 8.4.2 Basic Functions.................................................................................................... 8.4.3 Synchronization ................................................................................................... 8.4.4 PWM Mode.......................................................................................................... 8.4.5 Reset-Synchronized PWM Mode......................................................................... 8.4.6 Complementary PWM Mode ............................................................................... 8.4.7 Phase Counting Mode .......................................................................................... 8.4.8 Buffering.............................................................................................................. 8.4.9 ITU Output Timing .............................................................................................. Interrupts ........................................................................................................................... 8.5.1 Setting of Status Flags.......................................................................................... 8.5.2 Clearing of Status Flags ....................................................................................... 8.5.3 Interrupt Sources.................................................................................................. Usage Notes ...................................................................................................................... 191 191 194 199 201 204 204 206 208 211 214 216 218 219 220 221 223 225 227 228 228 231 232 232 234 243 245 249 252 261 263 269 272 272 274 275 276 8.2 8.3 8.4 8.5 8.6 Rev.3.00 Mar. 26, 2007 Page xv of xxii REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller................................................. 291 9.1 Overview........................................................................................................................... 9.1.1 Features................................................................................................................ 9.1.2 Block Diagram..................................................................................................... 9.1.3 TPC Pins .............................................................................................................. 9.1.4 Registers............................................................................................................... Register Descriptions ........................................................................................................ 9.2.1 Port A Data Direction Register (PADDR) ........................................................... 9.2.2 Port A Data Register (PADR).............................................................................. 9.2.3 Port B Data Direction Register (PBDDR) ........................................................... 9.2.4 Port B Data Register (PBDR) .............................................................................. 9.2.5 Next Data Register A (NDRA) ............................................................................ 9.2.6 Next Data Register B (NDRB)............................................................................. 9.2.7 Next Data Enable Register A (NDERA).............................................................. 9.2.8 Next Data Enable Register B (NDERB) .............................................................. 9.2.9 TPC Output Control Register (TPCR) ................................................................. 9.2.10 TPC Output Mode Register (TPMR) ................................................................... Operation .......................................................................................................................... 9.3.1 Overview.............................................................................................................. 9.3.2 Output Timing ..................................................................................................... 9.3.3 Normal TPC Output............................................................................................. 9.3.4 Non-Overlapping TPC Output............................................................................. 9.3.5 TPC Output Triggering by Input Capture ............................................................ Usage Notes ...................................................................................................................... 9.4.1 Operation of TPC Output Pins ............................................................................. 9.4.2 Note on Non-Overlapping Output........................................................................ 291 291 292 293 294 295 295 295 296 296 297 299 301 302 303 306 308 308 309 310 312 314 315 315 315 9.2 9.3 9.4 Section 10 Watchdog Timer............................................................................................. 317 10.1 Overview........................................................................................................................... 10.1.1 Features................................................................................................................ 10.1.2 Block Diagram..................................................................................................... 10.1.3 Pin Configuration................................................................................................. 10.1.4 Register Configuration......................................................................................... 10.2 Register Descriptions ........................................................................................................ 10.2.1 Timer Counter (TCNT)........................................................................................ 10.2.2 Timer Control/Status Register (TCSR)................................................................ 10.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 10.2.4 Notes on Register Access..................................................................................... 10.3 Operation .......................................................................................................................... 10.3.1 Watchdog Timer Operation ................................................................................. 10.3.2 Interval Timer Operation ..................................................................................... Rev.3.00 Mar. 26, 2007 Page xvi of xxii REJ09B0353-0300 317 317 318 318 319 319 319 320 322 324 326 326 327 10.3.3 Timing of Setting of Overflow Flag (OVF) ......................................................... 10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST)................................... 10.4 Interrupts ........................................................................................................................... 10.5 Usage Notes ...................................................................................................................... 328 329 329 330 Section 11 Serial Communication Interface ................................................................ 331 11.1 Overview........................................................................................................................... 11.1.1 Features................................................................................................................ 11.1.2 Block Diagram ..................................................................................................... 11.1.3 Input/Output Pins ................................................................................................. 11.1.4 Register Configuration......................................................................................... 11.2 Register Descriptions ........................................................................................................ 11.2.1 Receive Shift Register (RSR)............................................................................... 11.2.2 Receive Data Register (RDR) .............................................................................. 11.2.3 Transmit Shift Register (TSR) ............................................................................. 11.2.4 Transmit Data Register (TDR)............................................................................. 11.2.5 Serial Mode Register (SMR)................................................................................ 11.2.6 Serial Control Register (SCR).............................................................................. 11.2.7 Serial Status Register (SSR)................................................................................. 11.2.8 Bit Rate Register (BRR) ...................................................................................... 11.3 Operation........................................................................................................................... 11.3.1 Overview.............................................................................................................. 11.3.2 Operation in Asynchronous Mode ....................................................................... 11.3.3 Multiprocessor Communication........................................................................... 11.3.4 Synchronous Operation........................................................................................ 11.4 SCI Interrupts.................................................................................................................... 11.5 Usage Notes ...................................................................................................................... 331 331 333 334 335 336 336 336 337 337 338 341 345 349 358 358 360 369 376 384 385 391 391 391 392 393 393 394 394 396 397 397 398 399 Section 12 Smart Card Interface ..................................................................................... 12.1 Overview........................................................................................................................... 12.1.1 Features................................................................................................................ 12.1.2 Block Diagram ..................................................................................................... 12.1.3 Pin Configuration................................................................................................. 12.1.4 Register Configuration......................................................................................... 12.2 Register Descriptions ........................................................................................................ 12.2.1 Smart Card Mode Register (SCMR) .................................................................... 12.2.2 Serial Status Register (SSR)................................................................................. 12.3 Operation........................................................................................................................... 12.3.1 Overview.............................................................................................................. 12.3.2 Pin Connections ................................................................................................... 12.3.3 Data Format ......................................................................................................... Rev.3.00 Mar. 26, 2007 Page xvii of xxii REJ09B0353-0300 12.3.4 Register Settings .................................................................................................. 12.3.5 Clock.................................................................................................................... 12.3.6 Data Transfer Operations..................................................................................... 12.4 Usage Note........................................................................................................................ 401 403 405 411 Section 13 A/D Converter................................................................................................. 415 13.1 Overview........................................................................................................................... 13.1.1 Features................................................................................................................ 13.1.2 Block Diagram..................................................................................................... 13.1.3 Input Pins ............................................................................................................. 13.1.4 Register Configuration......................................................................................... 13.2 Register Descriptions ........................................................................................................ 13.2.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 13.2.2 A/D Control/Status Register (ADCSR) ............................................................... 13.2.3 A/D Control Register (ADCR) ............................................................................ 13.3 CPU Interface.................................................................................................................... 13.4 Operation .......................................................................................................................... 13.4.1 Single Mode (SCAN = 0) .................................................................................... 13.4.2 Scan Mode (SCAN = 1)....................................................................................... 13.4.3 Input Sampling and A/D Conversion Time ......................................................... 13.4.4 External Trigger Input Timing............................................................................. 13.5 Interrupts........................................................................................................................... 13.6 Usage Notes ...................................................................................................................... 415 415 416 417 418 419 419 420 422 423 424 424 426 428 429 430 430 435 435 436 436 437 438 Section 14 RAM .................................................................................................................. 14.1 Overview........................................................................................................................... 14.1.1 Block Diagram..................................................................................................... 14.1.2 Register Configuration......................................................................................... 14.2 System Control Register (SYSCR) ................................................................................... 14.3 Operation .......................................................................................................................... Section 15 ROM .................................................................................................................. 439 15.1 Overview........................................................................................................................... 439 15.2 Overview of Flash Memory .............................................................................................. 440 15.2.1 Features................................................................................................................ 440 15.2.2 Block Diagram..................................................................................................... 441 15.2.3 Pin Configuration................................................................................................. 442 15.2.4 Register Configuration......................................................................................... 442 15.3 Register Descriptions ........................................................................................................ 443 15.3.1 Flash Memory Control Register (FLMCR).......................................................... 443 15.3.2 Erase Block Register (EBR) ................................................................................ 447 Rev.3.00 Mar. 26, 2007 Page xviii of xxii REJ09B0353-0300 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.3.3 RAM Control Register (RAMCR) ....................................................................... 15.3.4 Flash Memory Status Register (FLMSR)............................................................. On-Board Programming Modes........................................................................................ 15.4.1 Boot Mode ........................................................................................................... 15.4.2 User Program Mode............................................................................................. Programming/Erasing Flash Memory ............................................................................... 15.5.1 Program Mode ..................................................................................................... 15.5.2 Program-Verify Mode.......................................................................................... 15.5.3 Erase Mode .......................................................................................................... 15.5.4 Erase-Verify Mode............................................................................................... Flash Memory Protection.................................................................................................. 15.6.1 Hardware Protection ............................................................................................ 15.6.2 Software Protection.............................................................................................. 15.6.3 Error Protection.................................................................................................... 15.6.4 NMI Input Disable Conditions............................................................................. Flash Memory Emulation by RAM................................................................................... Flash Memory PROM Mode............................................................................................. 15.8.1 PROM Mode Setting............................................................................................ 15.8.2 Memory Map ....................................................................................................... 15.8.3 PROM Mode Operation ....................................................................................... 15.8.4 Memory Read Mode ............................................................................................ 15.8.5 Auto-Program Mode ............................................................................................ 15.8.6 Auto-Erase Mode ................................................................................................. 15.8.7 Status Read Mode ................................................................................................ 15.8.8 PROM Mode Transition Time ............................................................................. 15.8.9 Notes on Memory Programming.......................................................................... Notes on Flash Memory Programming/Erasing................................................................ Mask ROM Overview ....................................................................................................... 15.10.1 Block Diagram ..................................................................................................... Notes on Ordering Mask ROM Version Chip................................................................... 449 451 452 455 460 462 463 464 466 466 468 468 470 471 473 474 475 475 476 476 479 482 484 485 487 488 488 494 494 495 Section 16 Clock Pulse Generator .................................................................................. 497 16.1 Overview........................................................................................................................... 16.1.1 Block Diagram ..................................................................................................... 16.2 Oscillator Circuit............................................................................................................... 16.2.1 Connecting a Crystal Resonator........................................................................... 16.2.2 External Clock Input ............................................................................................ 16.3 Duty Adjustment Circuit ................................................................................................... 16.4 Prescalers .......................................................................................................................... 16.5 Frequency Divider............................................................................................................. 16.5.1 Register Configuration......................................................................................... 497 498 498 499 501 504 504 504 504 Rev.3.00 Mar. 26, 2007 Page xix of xxii REJ09B0353-0300 16.5.2 Division Control Register (DIVCR) .................................................................... 505 16.5.3 Usage Notes ......................................................................................................... 506 Section 17 Power-Down State ......................................................................................... 507 17.1 Overview........................................................................................................................... 507 17.2 Register Configuration...................................................................................................... 509 17.2.1 System Control Register (SYSCR) ...................................................................... 509 17.2.2 Module Standby Control Register (MSTCR) ...................................................... 511 17.3 Sleep Mode ....................................................................................................................... 513 17.3.1 Transition to Sleep Mode..................................................................................... 513 17.3.2 Exit from Sleep Mode.......................................................................................... 513 17.4 Software Standby Mode.................................................................................................... 514 17.4.1 Transition to Software Standby Mode ................................................................. 514 17.4.2 Exit from Software Standby Mode ...................................................................... 514 17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode .. 515 17.4.4 Sample Application of Software Standby Mode.................................................. 516 17.4.5 Usage Note........................................................................................................... 516 17.5 Hardware Standby Mode .................................................................................................. 517 17.5.1 Transition to Hardware Standby Mode................................................................ 517 17.5.2 Exit from Hardware Standby Mode ..................................................................... 517 17.5.3 Timing for Hardware Standby Mode ................................................................... 518 17.6 Module Standby Function................................................................................................. 519 17.6.1 Module Standby Timing ...................................................................................... 519 17.6.2 Read/Write in Module Standby ........................................................................... 519 17.6.3 Usage Notes ......................................................................................................... 519 17.7 System Clock Output Disabling Function......................................................................... 520 Section 18 Electrical Characteristics.............................................................................. 521 18.1 Electrical Characteristics of Mask ROM Version............................................................. 18.1.1 Absolute Maximum Ratings ................................................................................ 18.1.2 DC Characteristics ............................................................................................... 18.1.3 AC Characteristics ............................................................................................... 18.1.4 A/D Conversion Characteristics........................................................................... 18.2 Electrical Characteristics of Flash Memory Version ........................................................ 18.2.1 Absolute Maximum Ratings ................................................................................ 18.2.2 DC Characteristics ............................................................................................... 18.2.3 AC Characteristics ............................................................................................... 18.2.4 A/D Conversion Characteristics........................................................................... 18.2.5 Flash Memory Characteristics ............................................................................. 18.3 Operational Timing........................................................................................................... 18.3.1 Bus Timing .......................................................................................................... Rev.3.00 Mar. 26, 2007 Page xx of xxii REJ09B0353-0300 521 521 522 530 535 536 536 537 543 548 549 552 552 18.3.2 18.3.3 18.3.4 18.3.5 18.3.6 Control Signal Timing ......................................................................................... Clock Timing ....................................................................................................... TPC and I/O Port Timing..................................................................................... ITU Timing .......................................................................................................... SCI Input/Output Timing ..................................................................................... 556 558 558 559 560 Appendix A Instruction Set .............................................................................................. 561 A.1 A.2 A.3 Instruction List .................................................................................................................. 561 Operation Code Maps ....................................................................................................... 577 Number of States Required for Execution ........................................................................ 580 Appendix B Internal I/O Register Field ........................................................................ 590 B.1 B.2 Addresses .......................................................................................................................... 590 Function ............................................................................................................................ 597 Appendix C I/O Block Diagrams.................................................................................... 655 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 Port 1 Block Diagram ....................................................................................................... Port 2 Block Diagram ....................................................................................................... Port 3 Block Diagram ....................................................................................................... Port 5 Block Diagram ....................................................................................................... Port 6 Block Diagram ....................................................................................................... Port 7 Block Diagram ....................................................................................................... Port 8 Block Diagram ....................................................................................................... Port 9 Block Diagram ....................................................................................................... Port A Block Diagram....................................................................................................... Port B Block Diagram....................................................................................................... 655 656 657 658 659 661 662 664 668 671 Appendix D Pin States ....................................................................................................... 674 D.1 D.2 Port States in Each Mode .................................................................................................. 674 Pin States at Reset ............................................................................................................. 676 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode................................................................. 679 Appendix F Product Lineup ............................................................................................. 680 Appendix G Package Dimensions ................................................................................... 681 Rev.3.00 Mar. 26, 2007 Page xxi of xxii REJ09B0353-0300 Rev.3.00 Mar. 26, 2007 Page xxii of xxii REJ09B0353-0300 Section 1 Overview Section 1 Overview 1.1 Overview The H8/3039 Group comprises microcomputers (MCUs) that integrate system supporting functions together with an H8/300H CPU core featuring an original Renesas Technology architecture. The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series. The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, I/O ports, and other facilities. The H8/3039 Group consists of four models: the H8/3039 with 128 kbytes of ROM and 4 kbytes of RAM, the H8/3038 with 64 kbytes of ROM and 2 kbytes of RAM, the H8/3037 with 32 kbytes of ROM and 1 kbytes of RAM, and the H8/3036 with 16 kbytes of ROM and 512 bytes of RAM. The five MCU operating modes offer a choice of expanded mode, single-chip mode and address space size. In addition to the mask-ROM version of the H8/3039 Group, an F-ZTATTM version with an onchip flash memory that can be freely programmed and reprogrammed by the user after the board is installed is also available. This version enables users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. Table 1.1 summarizes the features of the H8/3039 Group. Note: F-ZTAT is a trademark of Renesas Technology Corp. Rev.3.00 Mar. 26, 2007 Page 1 of 682 REJ09B0353-0300 Section 1 Overview Table 1.1 Feature CPU Features Description Upward-compatible with the H8/300 CPU at the object-code level General-register machine * Sixteen 16-bit general registers (also useable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation * * * Maximum clock rate: 18 MHz Add/subtract: 111 ns Multiply/divide: 778 ns Two CPU operating modes * * Normal mode (64-kbyte address space) Advanced mode (16-Mbyte address space) Instruction features * * * * * 8/16/32-bit data transfer, arithmetic, and logic instructions Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits) Signed and unsigned divide instructions (16 bits / 8 bits, 32 bits / 16 bits) Bit accumulator function Bit manipulation instructions with register-indirect specification of bit positions Rev.3.00 Mar. 26, 2007 Page 2 of 682 REJ09B0353-0300 Section 1 Overview Feature Memory Description H8/3039 * * ROM: 128 kbytes RAM: 4 kbytes H8/3038 * * ROM: 64 kbytes RAM: 2 kbytes H8/3037 * * ROM: 32 kbytes RAM: 1 kbyte H8/3036 * * Interrupt controller * * * Bus controller * * * 16-bit integrated timer unit (ITU) * * * * * * * * * ROM: 16 kbytes RAM: 512 bytes Five external interrupt pins: NMI, IRQ0, IRQ1, IRQ4, IRQ5 25 internal interrupts Three selectable interrupt priority levels Address space can be partitioned into eight areas, with independent bus specifications in each area Two-state or three-state access selectable for each area Selection of four wait modes Five 16-bit timer channels, capable of processing up to 12 pulse outputs or 10 pulse inputs 16-bit timer counter (channels 0 to 4) Two multiplexed output compare/input capture pins (channels 0 to 4) Operation can be synchronized (channels 0 to 4) PWM mode available (channels 0 to 4) Phase counting mode available (channel 2) Buffering available (channels 3 and 4) Reset-synchronized PWM mode available (channels 3 and 4) Complementary PWM mode available (channels 3 and 4) Rev.3.00 Mar. 26, 2007 Page 3 of 682 REJ09B0353-0300 Section 1 Overview Feature Programmable timing pattern controller (TPC) Description * * * Watchdog timer (WDT), 1 channel * * * Serial communication interface (SCI), 2 channels A/D converter * * * * * * * * * I/O ports Operating modes * * Maximum 15-bit pulse output, using ITU as time base Up to three 4-bit pulse output groups and one 3-bit pulse output group (or one 15-bit group, one 8-bit group, or one 7-bit group) Non-overlap mode available Reset signal can be generated by overflow Reset signal can be output externally (However, not available with the F-ZTAT version.) Usable as an interval timer Selection of asynchronous or synchronous mode Full duplex: can transmit and receive simultaneously On-chip baud-rate generator Smart card interface functions added (SCI0 only) Resolution: 10 bits Eight channels, with selection of single or scan mode Variable analog conversion voltage range Sample-and-hold function Can be externally triggered 55 input/output pins 8 input-only pins Address Space 1 Mbyte 16 Mbytes 1 Mbyte 64 kbytes 1 Mbyte Address Pins A0 to A19 A23 to A0 A0 to A19 -- -- Bus Width 8 bits 8 bits 8 bits -- -- Five MCU operating modes Mode Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 * Power-down state * * * * * On-chip ROM is disabled in modes 1 and 3 Sleep mode Software standby mode Hardware standby mode Module standby function Programmable System clock frequency division Rev.3.00 Mar. 26, 2007 Page 4 of 682 REJ09B0353-0300 Section 1 Overview Feature Other features Product lineup Description * On-chip clock oscillator Model (3 V)* HD64F3039VF HD64F3039VTE HD6433039VF HD6433039VTE HD6433038VF HD6433038VTE HD6433037VF HD6433037VTE HD6433036VF HD6433036VTE Package 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) Mask ROM Mask ROM Mask ROM Mask ROM ROM Flash memory Model (5 V) HD64F3039F HD64F3039TE HD6433039F HD6433039TE HD6433038F HD6433038TE HD6433037F HD6433037TE HD6433036F HD6433036TE Note: * There are two 3 V versions: one with VCC = 2.7 V to 5.5 V and = 2 to 8 MHz, and one with VCC = 3.0 V to 5.5 V and = 2 to 10 MHz. However, there is only one flash memory version, with VCC = 3.0 to 5.5 V and = 2 to 10 MHz. Rev.3.00 Mar. 26, 2007 Page 5 of 682 REJ09B0353-0300 Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the H8/3039 Group. P37/D7 P36/D6 P35/D5 P34/D4 P33/D3 P32/D2 P31/D1 P30/D0 VCC VCC VSS VSS VSS Port 3 Address bus MD2 MD1 MD0 EXTAL XTAL STBY RES RESO/FWE* NMI Data bus (upper) Data bus (lower) Clock osc. Bus controller Port 5 Port 2 Port 1 H8/300H CPU P53/A19 P52/A18 P51/A17 P50/A16 P65/WR P64/RD P63/AS P60/WAIT Port 6 ROM (Flash memory, mask ROM) Interrupt controller P27/A15 P26/A14 P25/A13 P24/A12 P23/A11 P22/A10 P21/A9 P20/A8 P17/A7 P16/A6 P15/A5 P14/A4 P13/A3 P12/A2 P11/A1 P10/A0 RAM Watchdog timer (WDT) Serial communication interface (SCI) x 2 channel P81/IRQ1 P80/IRQ0 16-bit integrated timer unit (ITU) Port 8 Port B PB7/TP15/ADTRG PB5/TP13/TOCXB4 PB4/TP12/TOCXA4 PB3/TP11/TIOCB4 PB2/TP10/TIOCA4 PB1/TP9/TIOCB3 PB0/TP8/TIOCA3 Port A PA7/TP7/TIOCB2/A20 PA6/TP6/TIOCA2/A21 PA5/TP5/TIOCB1/A22 PA4/TP4/TIOCA1/A23 PA3/TP3/TIOCB0/TCLKD PA2/TP2/TIOCA0/TCLKC PA1/TP1/TCLKB PA0/TP0/TCLKA AVCC AVSS Port 7 P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0 Note: * Mask ROM: RESO Flash memory: FWE Figure 1.1 Block Diagram Rev.3.00 Mar. 26, 2007 Page 6 of 682 REJ09B0353-0300 Port 9 Programmable timing pattern controller (TPC) A/D converter P95/SCK1/IRQ5 P94/SCK0/IRQ4 P93/RxD1 P92/RxD0 P91/TxD1 P90/TxD0 Section 1 Overview 1.3 1.3.1 Pin Description Pin Arrangement Figure 1.2 shows the pin arrangement of the H8/3039 Group. PA3/TP3/TIOCB0/TCLKD PA2/TP2/TIOCA0/TCLKC PA7/TP7/TIOCB2/A20 PA6/TP6/TIOCA2/A21 PA5/TP5/TIOCB1/A22 PA4/TP4/TIOCA1/A23 PA1/TP1/TCLKB PA0/TP0/TCLKA P95/SCK1/IRQ5 P93/RxD1 P91/TxD1 P81/IRQ1 P80/IRQ0 P77/AN7 P76/AN6 P75/AN5 P74/AN4 P73/AN3 62 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 TIOCA3/TP8/PB0 TIOCB3/TP9/PB1 TIOCA4/TP10/PB2 TIOCB4/TP11/PB3 TOCXA4/TP12/PB4 TOCXB4/TP13/PB5 MD2 ADTRG/TP15/PB7 TxD0/P90 RxD0/P92 IRQ4/SCK0/P94 VSS D0/P30 D1/P31 D2/P32 D3/P33 D4/P34 D5/P35 D6/P36 D7/P37 61 P72/AN2 AVcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 60 59 58 57 56 55 54 53 52 Top view (FP-80A, TFP-80C) 51 50 49 48 47 46 45 44 43 42 41 P71/AN1 P70/AN0 AVSS RESO/FWE* P65/WR P64/RD P63/AS VCC XTAL EXTAL VSS NMI RES STBY MD1 MD0 P60/WAIT P53/A19 P52/A18 VCC A0/P10 A1/P11 A2/P12 A3/P13 A4/P14 A5/P15 A6/P16 A7/P17 A8/P20 A9/P21 A10/P22 A11/P23 A12/P24 A13/P25 A14/P26 A15/P27 A16/P50 Note: * Mask ROM: RESO Flash memory: FWE Figure 1.2 Pin Arrangement (FP-80A, TFP-80C Top View) Rev.3.00 Mar. 26, 2007 Page 7 of 682 REJ09B0353-0300 A17/P51 VSS Section 1 Overview 1.3.2 Pin Functions Pin Assignments in Each Mode Table 1.2 lists the FP-80A and TFP-80C pin assignments in each mode. Table 1.2 FP-80A and TFP-80C Pin Assignments in Each Mode Pin Name Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Mode 1 PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 MD2 PB7/TP15/ ADTRG P90/TxD0 P92/RxD0 P94/SCK0/ IRQ4 VSS D0 D1 D2 D3 D4 Mode 3 PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 MD2 PB7/TP15/ ADTRG P90/TxD0 P92/RxD0 P94/SCK0/ IRQ4 VSS D0 D1 D2 D3 D4 Mode 5 PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 MD2 PB7/TP15/ ADTRG P90/TxD0 P92/RxD0 P94/SCK0/ IRQ4 VSS D0 D1 D2 D3 D4 Mode 6 PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 MD2 PB7/TP15/ ADTRG P90/TxD0 P92/RxD0 P94/SCK0/ IRQ4 VSS P30 P31 P32 P33 P34 Mode 7 PB0/TP8/ TIOCA3 PB1/TP9/ TIOCB3 PB2/TP10/ TIOCA4 PB3/TP11/ TIOCB4 PB4/TP12/ TOCXA4 PB5/TP13/ TOCXB4 MD2 PB7/TP15/ ADTRG P90/TxD0 P92/RxD0 P94/SCK0/ IRQ4 VSS P30 P31 P32 P33 P34 PROM Mode Flash memory NC NC NC NC NC NC VSS NC NC VSS NC VSS I/O0 I/O1 I/O2 I/O3 I/O4 Rev.3.00 Mar. 26, 2007 Page 8 of 682 REJ09B0353-0300 Section 1 Overview Pin Name Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Mode 1 D5 D6 D7 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 P60/WAIT MD0 MD1 Mode 3 D5 D6 D7 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 P60/WAIT MD0 MD1 Mode 5 D5 D6 D7 VCC P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 VSS P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P50/A16 P51/A17 P52/A18 P53/A19 P60/WAIT MD0 MD1 Mode 6 P35 P36 P37 VCC P10 P11 P12 P13 P14 P15 P16 P17 VSS P20 P21 P22 P23 P24 P25 P26 P27 P50 P51 P52 P53 P60 MD0 MD1 Mode 7 P35 P36 P37 VCC P10 P11 P12 P13 P14 P15 P16 P17 VSS P20 P21 P22 P23 P24 P25 P26 P27 P50 P51 P52 P53 P60 MD0 MD1 PROM Mode Flash memory I/O5 I/O6 I/O7 VCC A0 A1 A2 A3 A4 A5 A6 A7 VSS A8 A9 A10 A11 A12 A13 A14 A15 A16 VSS VSS VSS NC VSS VSS NC Rev.3.00 Mar. 26, 2007 Page 9 of 682 REJ09B0353-0300 Section 1 Overview Pin Name Pin No. 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 Mode 1 STBY RES NMI VSS EXTAL XTAL VCC AS RD WR RESO/ FWE* AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P80/IRQ0 P81/IRQ1 P91/TxD1 P93/RxD1 P95/SCK1/ IRQ5 PA0/TP0/ TCLKA Mode 3 STBY RES NMI VSS EXTAL XTAL VCC AS RD WR RESO/ FWE* AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P80/IRQ0 P81/IRQ1 P91/TxD1 P93/RxD1 P95/SCK1/ IRQ5 PA0/TP0/ TCLKA Mode 5 STBY RES NMI VSS EXTAL XTAL VCC AS RD WR RESO/ FWE* AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P80/IRQ0 P81/IRQ1 P91/TxD1 P93/RxD1 P95/SCK1/ IRQ5 PA0/TP0/ TCLKA Mode 6 STBY RES NMI VSS EXTAL XTAL VCC P63 P64 P65 RESO/ FWE* AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P80/IRQ0 P81/IRQ1 P91/TxD1 P93/RxD1 P95/SCK1/ IRQ5 PA0/TP0/ TCLKA Mode 7 STBY RES NMI VSS EXTAL XTAL VCC P63 P64 P65 RESO/ FWE* AVSS P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7 AVCC P80/IRQ0 P81/IRQ1 P91/TxD1 P93/RxD1 P95/SCK1/ IRQ5 PA0/TP0/ TCLKA PROM Mode Flash memory VCC RES VCC VSS EXTAL XTAL VCC NC NC VCC FWE VSS NC NC NC NC NC NC NC NC VCC VSS VSS NC NC VCC CE Rev.3.00 Mar. 26, 2007 Page 10 of 682 REJ09B0353-0300 Section 1 Overview Pin Name Pin No. 74 75 Mode 1 PA1/TP1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2 Mode 3 PA1/TP1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1/A23 PA5/TP5/ TIOCB1/A22 PA6/TP6/ TIOCA2/A21 A20 Mode 5 PA1/TP1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2 Mode 6 PA1/TP1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2 Mode 7 PA1/TP1/ TCLKB PA2/TP2/ TIOCA0/ TCLKC PA3/TP3/ TIOCB0/ TCLKD PA4/TP4/ TIOCA1 PA5/TP5/ TIOCB1 PA6/TP6/ TIOCA2 PA7/TP7/ TIOCB2 PROM Mode Flash memory OE WE 76 NC 77 78 79 80 NC NC NC NC Notes: Pins marked NC should be left unconnected. For details about PROM mode see section 15, ROM. * Mask ROM: RESO Flash Memory: FWE Rev.3.00 Mar. 26, 2007 Page 11 of 682 REJ09B0353-0300 Section 1 Overview 1.4 Pin Functions Table 1.3 summarizes the pin functions. Table 1.3 Type Power Pin Functions Symbol VCC Pin No. 21, 53 12, 30, 50 52 I/O Input Name and Function Power: For connection to the power supply. Connect all VCC pins to the system power supply. Ground: For connection to ground (0 V). Connect all VSS pins to the 0-V system power supply. For connection to a crystal resonator For examples of crystal resonator and external clock input, see section 16, Clock Pulse Generator. For connection to a crystal resonator or input of an external clock signal. For examples of crystal resonator and external clock input, see section 16, Clock Pulse Generator. System clock: Supplies the system clock to external devices Mode 2 to mode 0: For setting the operating mode, as follows. These pins should not be changed during operation. MD2 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Operating Mode -- Mode 1 -- Mode 3 -- Mode 5 Mode 6 Mode 7 VSS Input Clock XTAL Input EXTAL 51 Input Operating mode control MD2, MD1, MD0 46 7, 45, 44 Output Input Rev.3.00 Mar. 26, 2007 Page 12 of 682 REJ09B0353-0300 Section 1 Overview Type System control Symbol RES RESO/ FWE Pin No. 48 57 I/O Input Output/ Input Name and Function Reset input: When driven low, this pin resets the chip Reset output (Mask ROM version): Outputs WDT-generated reset signal to an external device. Write enable signal (F-ZTAT version): Flash memory write control signal. STBY Interrupts NMI 47 49 Input Input Input Output Standby: When driven low, this pin forces a transition to hardware standby mode Nonmaskable interrupt: Requests a nonmaskable interrupt Interrupt request 5, 4, 1, 0: Maskable interrupt request pins Address bus: Outputs address signals IRQ5, IRQ4 72, 11, IRQ1, IRQ0 69, 68 Address bus A23 to A20, A19 to A8, A7 to A0 D7 to D0 AS RD WR 77 to 80, 42 to 31, 29 to 22 20 to 13 54 55 56 Data bus Bus control Input/ output Output Output Output Data bus: Bidirectional data bus Address strobe: Goes low to indicate valid address output on the address bus Read: Goes low to indicate reading from the external address space. Write: Goes low to indicate writing to the external address space indicates valid data on the data bus. Wait: Requests insertion of wait states in bus cycles during access to the external address space. Clock input A to D: External clock inputs Input capture/output compare A4 to A0: GRA4 to GRA0 output compare or input capture, or PWM output Input capture/output compare B4 to B0 GRB4 to GRB0 output compare or input capture, or PWM output Output compare XA4: PWM output Output compare XB4: PWM output WAIT 43 Input 16-bit integrated timer unit (ITU) TCLKD to TCLKA TIOCA4 to TIOCA0 TIOCB4 to TIOCB0 TOCXA4 TOCXB4 76 to 73 3, 1, 79, 77, 75 4, 2, 80, 78, 76 5 6 Input Input/ Output Input/ output Output Output Rev.3.00 Mar. 26, 2007 Page 13 of 682 REJ09B0353-0300 Section 1 Overview Type Symbol Pin No. I/O Output Name and Function TPC output 15, 13 to 0 : Pulse output Programmable TP15, 8, 6 to 1 timing pattern TP13 to TP0 80 to 73 controller (TPC) Serial communication interface (SCI) TxD1, TxD0 RxD1, RxD0 SCK1, SCK0 A/D converter ADTRG AVCC 70, 9 71, 10 72, 11 Output Input Input/ output Input Input Input Transmit data:(channels 0 and 1): SCI data output Receive data:(channels 0 and 1): SCI data input Serial clock:(channels 0 and 1): SCI clock input/output Analog 7 to 0: Analog input pins A/D trigger: External trigger input for starting A/D conversion Power supply pin and reference voltage input pin for the A/D converter. Connect to the system power supply when not using the A/D converter. Ground pin for the A/D converter. Connect to system power-supply (0 V). Port 1: Eight input/output pins. The direction of each pin can be selected in the port 1 data direction register (P1DDR). Port 2: Eight input/output pins. The direction of each pin can be selected in the port 2 data direction register (P2DDR). Port 3: Eight input/output pins. The direction of each pin can be selected in the port 3 data direction register (P3DDR). Port 5: Four input/output pins. The direction of each pin can be selected in the port 5 data direction register (P5DDR). Port 6: Four input/output pins. The direction of each pin can be selected in the port 6 data direction register (P6DDR). Port 7: Eight input pins Port 8: Two input/output pins. The direction of each pin can be selected in the port 8 data direction register (P8DDR). AN7 to AN0 66 to 59 8 67 AVSS I/O ports P17 to P10 58 29 to 22 Input Input/ output Input/ output Input/ output Input/ output Input/ output Input Input/ output P27 to P20 38 to 31 P37 to P30 20 to 13 P53 to P50 42 to 39 P65 to P63, 56 to 54, P60 43 P77 to P70 P81, P80 66 to 59 69, 68 Rev.3.00 Mar. 26, 2007 Page 14 of 682 REJ09B0353-0300 Section 1 Overview Type I/O ports Symbol P95 to P90 PA7 to PA0 PB7, PB5 to PB0 Pin No. 72, 11 71, 10 70, 9 80 to 73 I/O Input/ output Input/ output Input/ output Name and Function Port 9: Six input/output pins. The direction of each pin can be selected in the port 9 data direction register (P9DDR). Port A: Eight input/output pins. The direction of each pin can be selected in the port A data direction register (PADDR). Port B: Seven input/output pins. The direction of each pin can be selected in the port B data direction register (PBDDR). 8, 6to1 Rev.3.00 Mar. 26, 2007 Page 15 of 682 REJ09B0353-0300 Section 1 Overview Rev.3.00 Mar. 26, 2007 Page 16 of 682 REJ09B0353-0300 Section 2 CPU Section 2 CPU 2.1 Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. 2.1.1 Features The H8/300H CPU has the following features. * Upward compatibility with H8/300 CPU Can execute H8/300 series object programs without alteration * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-two basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16, ERn) or @(d:24, ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, or @aa:24] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8, PC) or @(d:16, PC)] Memory indirect [@@aa:8] * 16-Mbyte linear address space * High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 8 x 8-bit register-register multiply: 16 / 8-bit register-register divide: 18 MHz 778 ns 778 ns Rev.3.00 Mar. 26, 2007 Page 17 of 682 REJ09B0353-0300 8/16/32-bit register-register add/subtract: 111 ns Section 2 CPU 16 x 16-bit register-register multiply: 32 / 16-bit register-register divide: * Two CPU operating modes Normal mode Advanced mode * Low-power mode 1222 ns 1222 ns Transition to power-down state by SLEEP instruction 2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8/300H has the following enhancements. * More general registers Eight 16-bit registers have been added. * Expanded address space Advanced mode supports a maximum 16-Mbyte address space. Normal mode supports the same 64-kbyte address space as the H8/300 CPU. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Data transfer, arithmetic, and logic instructions can operate on 32-bit data. Signed multiply/divide instructions and other instructions have been added. Rev.3.00 Mar. 26, 2007 Page 18 of 682 REJ09B0353-0300 Section 2 CPU 2.2 CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports up to 16 Mbytes. See figure 2.1. Unless specified otherwise, all descriptions in this manual refer to advanced mode. Maximum 64 kbytes, program and data areas combined Normal mode CPU operating modes Maximum 16 Mbytes, program and data areas combined Advanced mode Figure 2.1 CPU Operating Modes Rev.3.00 Mar. 26, 2007 Page 19 of 682 REJ09B0353-0300 Section 2 CPU 2.3 Address Space The maximum address space of the H8/300H CPU is 16 Mbytes. This LSI allows selection of a normal mode and advanced mode 1-Mbyte mode or 16-Mbyte mode for the address space depending on the MCU operation mode. Figure 2.2 shows the address ranges of the H8/3039 Group. For further details see section 3.6, Memory Map in Each Operating Mode. The 1-Mbyte operating mode uses 20-bit addressing. The upper 4 bits of effective addresses are ignored. H'0000 H'00000 H'000000 H'FFFF H'FFFFF H'FFFFFF (a) 1-Mbyte mode 1. Normal mode (64-Kbyte mode) 2. Advanced mode (b) 16-Mbyte mode Figure 2.2 Memory Map Rev.3.00 Mar. 26, 2007 Page 20 of 682 REJ09B0353-0300 Section 2 CPU 2.4 2.4.1 Register Configuration Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control Registers (CR) 23 PC 76543210 CCR I UI H U N Z V C Legend: SP: Stack pointer PC: Program counter CCR: Condition code register Interrupt mask bit I: User bit or interrupt mask bit UI: Half-carry flag H: User bit U: Negative flag N: Zero flag Z: Overflow flag V: Carry flag C: 0 E0 E1 E2 E3 E4 E5 E6 E7 (SP) 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Figure 2.3 CPU Registers Rev.3.00 Mar. 26, 2007 Page 21 of 682 REJ09B0353-0300 Section 2 CPU 2.4.2 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or as address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2.4 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) E0 to E7 * 8-bit registers ER registers ER0 to ER7 R registers R0 to R7 RH registers R0H to R7H RL registers R0L to R7L Figure 2.4 Usage of General Registers Rev.3.00 Mar. 26, 2007 Page 22 of 682 REJ09B0353-0300 Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. Free area SP (ER7) Stack area Figure 2.5 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC) and the 8-bit condition code register (CCR). Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word) or a multiple of 2 bytes, so the least significant PC bit is ignored. When an instruction is fetched, the least significant PC bit is regarded as 0. Condition Code Register (CCR) This 8-bit register contains internal CPU status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. This bit can also be used as an interrupt mask bit. For details see section 5, Interrupt Controller. Rev.3.00 Mar. 26, 2007 Page 23 of 682 REJ09B0353-0300 Section 2 CPU Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave flag bits unchanged. Operations can be performed on CCR by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used by conditional branch (Bcc) instructions. For the action of each instruction on the flag bits, see appendix A.1, Instruction List. For the I and UI bits, see section 5, Interrupt Controller. 2.4.4 Initial CPU Register Values In reset exception handling, PC is initialized to a value loaded from the vector table, and the I bit in CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer must therefore be initialized by an MOV.L instruction executed immediately after a reset. Rev.3.00 Mar. 26, 2007 Page 24 of 682 REJ09B0353-0300 Section 2 CPU 2.5 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figures 2.6 and 2.7 show the data formats in general registers. General Register Data Type Data Format 7 0 Don't care 7 0 1-bit data RnH 76543210 1-bit data RnL 7 Don't care 43 0 76543210 4-bit BCD data RnH Upper digit Lower digit Don't care 7 43 0 4-bit BCD data RnL 7 Don't care Upper digit Lower digit 0 Don't care LSB 7 0 LSB Don't care MSB Byte data RnH MSB Byte data RnL Legend: RnH: General register RH RnL: General register RL Figure 2.6 General Register Data Formats Rev.3.00 Mar. 26, 2007 Page 25 of 682 REJ09B0353-0300 Section 2 CPU Data Type General Register Data Format 15 0 LSB Word data Rn MSB 15 0 LSB 16 15 0 LSB Word data En MSB 31 Longword data ERn MSB Legend: ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least significant bit Figure 2.7 General Register Data Formats Rev.3.00 Mar. 26, 2007 Page 26 of 682 REJ09B0353-0300 Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address Data Format 7 1-bit data Byte data Word data Address L Address L Address 2m Address 2m + 1 Address 2n Longword data Address 2n + 1 Address 2n + 2 Address 2n + 3 MSB 0 6 5 4 3 2 1 0 LSB 7 MSB MSB LSB LSB Figure 2.8 Memory Data Formats When ER7 (SP) is used as an address register to access the stack, the operand size should be word size or longword size. Rev.3.00 Mar. 26, 2007 Page 27 of 682 REJ09B0353-0300 Section 2 CPU 2.6 2.6.1 Instruction Set Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified as shown in table 2.1. Table 2.1 Function Data transfer Arithmetic operations Logic operations Shift operations Bit manipulation Branch System control Block data transfer Instruction Classification Instruction MOV, PUSH* , POP* , MOVTPE* , MOVFPE* 1 1 2 2 Types 3 18 4 8 14 5 9 1 Total 62 types ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, MULXS, DIVXU, DIVXS, CMP, NEG, EXTS, EXTU AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc* , JMP, BSR, JSR, RTS TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV 3 Notes: 1. POP.W Rn is identical to MOV.W @SP+, Rn. PUSH.W Rn is identical to MOV.W Rn, @-SP. POP.L ERn is identical to MOV.L @SP+, Rn. PUSH.L ERn is identical to MOV.L Rn, @-SP. 2. These instructions are not available on the H8/3039 Group. 3. Bcc is a generic branching instruction. Rev.3.00 Mar. 26, 2007 Page 28 of 682 REJ09B0353-0300 Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Addressing Modes @ERn+/@-ERn @(d:24, ERn) @(d:16,ERn) Function Instruction @ERn #xx @(d:16,PC) @(d:8, PC) @@aa:8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- @aa:16 @aa:24 Data transfer MOV POP, PUSH MOVFPE, MOVTPE BWL BWL BWL BWL BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- BWL BWL -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL -- -- -- -- -- -- -- -- Arithmetic ADD, CMP operations SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, MULXS, DIVXU, DIVXS NEG EXTU, EXTS Logic AND, OR, operations XOR NOT Shift instructions Bit manipulation Branch Bcc, BSR JMP, JSR RTS BWL BWL WL BWL B -- -- -- -- B L BWL B BW -- -- BWL WL -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- BWL BWL B -- -- -- -- -- -- -- -- -- -- Rev.3.00 Mar. 26, 2007 Page 29 of 682 REJ09B0353-0300 Implied @aa:8 Rn Section 2 CPU Addressing Modes @ERn+/@-ERn @(d:24, ERn) @(d:16,ERn) Function Instruction @ERn #xx @(d:16,PC) @(d:8, PC) @@aa:8 -- -- -- -- -- -- -- -- @aa:16 @aa:24 System control TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP -- -- -- B -- B -- -- -- -- -- B B -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Block data transfer BW Legend: B: Byte W: Word L: Longword Rev.3.00 Mar. 26, 2007 Page 30 of 682 REJ09B0353-0300 Implied @aa:8 Rn Section 2 CPU 2.6.3 Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined as follows. Operation Notation Rd Rs Rn ERn (EAd) (EAs) CCR N Z V C PC SP #IMM disp + - x / :3/:8/:16/:24 Note: * General register (destination)* General register (source)* General register* General register (32-bit register or address register) Destination operand Source operand Condition code register N (negative) flag of CCR Z (zero) flag of CCR V (overflow) flag of CCR C (carry) flag of CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move NOT (logical complement) 3-, 8-, 16-, or 24-bit length General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit data or address registers (ER0 to ER7). Rev.3.00 Mar. 26, 2007 Page 31 of 682 REJ09B0353-0300 Section 2 CPU Table 2.3 Instruction MOV Data Transfer Instructions Size* B/W/L Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE MOVTPE POP B B W/L (EAs) Rd Cannot be used in the H8/3039 Group. Rs (EAs) Cannot be used in the H8/3039 Group. @SP+ Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. Similarly, POP.L ERn is identical to MOV.L @SP+, ERn. PUSH W/L Rn @-SP Pushes a general register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. Similarly, PUSH.L ERn is identical to MOV.L ERn, @-SP. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev.3.00 Mar. 26, 2007 Page 32 of 682 REJ09B0353-0300 Section 2 CPU Table 2.4 Instruction ADD, SUB Arithmetic Operation Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from data in a general register. Use the SUBX or ADD instruction.) B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry on data in two general registers, or on immediate data and data in a general register. B/W/L Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) L B Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to CCR to produce 4-bit BCD data. B/W Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. ADDX, SUBX INC, DEC ADDS, SUBS DAA, DAS MULXU MULXS B/W Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev.3.00 Mar. 26, 2007 Page 33 of 682 REJ09B0353-0300 Section 2 CPU Instruction DIVXU Size* B/W Function Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. DIVXS B/W Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. CMP B/W/L Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR according to the result. NEG B/W/L 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. EXTS W/L Rd (sign extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by extending the sign bit. EXTU W/L Rd (zero extension) Rd Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by padding with zeros. Note: * Size refers to the operand size. B: Byte W: Word L: Longword Rev.3.00 Mar. 26, 2007 Page 34 of 682 REJ09B0353-0300 Section 2 CPU Table 2.5 Instruction AND Logic Operation Instructions Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. NOT Note: * B/W/L Rd Rd Takes the one's complement of general register contents. Size refers to the operand size. B: Byte W: Word L: Longword Table 2.6 Instruction SHAL, SHAR SHLL, SHLR ROTL, ROTR ROTXL, ROTXR Note: * Shift Instructions Size* B/W/L B/W/L B/W/L B/W/L Function Rd (shift) Rd Performs an arithmetic shift on general register contents. Rd (shift) Rd Performs a logical shift on general register contents. Rd (rotate) Rd Rotates general register contents. Rd (rotate) Rd Rotates general register contents through the carry bit. Size refers to the operand size. B: Byte W: Word L: Longword Rev.3.00 Mar. 26, 2007 Page 35 of 682 REJ09B0353-0300 Section 2 CPU Table 2.7 Instruction BSET Bit Manipulation Instructions Size* B Function 1 ( BCLR B 0 ( BNOT B ( BTST B ( BAND B C ( BIAND B C [ ( BOR B C ( BIOR B C [ ( Rev.3.00 Mar. 26, 2007 Page 36 of 682 REJ09B0353-0300 Section 2 CPU Instruction BXOR Size* B Function C ( Rev.3.00 Mar. 26, 2007 Page 37 of 682 REJ09B0353-0300 Section 2 CPU Table 2.8 Instruction Bcc Branching Instructions Size -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine Rev.3.00 Mar. 26, 2007 Page 38 of 682 REJ09B0353-0300 Section 2 CPU Table 2.9 Instruction TRAPA RTE SLEEP LDC System Control Instructions Size* -- -- -- B/W Function Starts trap-instruction exception handling Returns from an exception-handling routine Causes a transition to the power-down state (EAs) CCR Moves the source operand contents to the condition code register. The condition code register size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR (EAd) Transfers the CCR contents to a destination location. The condition code register size is one byte, but in transfer to memory, data is written by word access. ANDC ORC XORC NOP Note: * B B B -- CCR #IMM CCR Logically ANDs the condition code register with immediate data. CCR #IMM CCR Logically ORs the condition code register with immediate data. CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data. PC + 2 PC Only increments the program counter. Size refers to the operand size. B: Byte W: Word Rev.3.00 Mar. 26, 2007 Page 39 of 682 REJ09B0353-0300 Section 2 CPU Table 2.10 Block Transfer Instruction Instruction EEPMOV.B Size -- Function if R4L 0 then repeat until else next; EEPMOV.W if R4 0 then repeat until else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: Size of block (bytes) ER5: Starting source address ER6: Starting destination address Execution of the next instruction begins as soon as the transfer is completed. @ER5+ @ER6+, R4 - 1 R4 R4 = 0 @ER5+ @ER6+, R4L - 1 R4L R4L = 0 2.6.4 Basic Instruction Formats The H8/300H instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (OP field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first 4 bits of the instruction. Some instructions have two operation fields. Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. A 24-bit address or displacement is treated as 32-bit data in which the first 8 bits are 0 (H'00). Condition Field: Specifies the branching condition of Bcc instructions. Rev.3.00 Mar. 26, 2007 Page 40 of 682 REJ09B0353-0300 Section 2 CPU Figure 2.9 shows examples of instruction formats. Operation field only op Operation field and register fields op rn rm ADD.B Rn, Rm, etc. NOP, RTS, etc. Operation field, register fields, and effective address extension op EA (disp) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:8 rn rm MOV.B @(d:16, Rn), Rm Figure 2.9 Instruction Formats 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, BST, and BIST instructions read a byte of data, modify a bit in the byte, then write the byte back. Care is required when these instructions are used to access registers with write-only bits, or to access ports. The BCLR instruction can be used to clear flags in the on-chip registers. In an interrupt-handling routine, for example, if it is known that the flag is set to 1, it is not necessary to read the flag ahead of time. 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except programcounter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute (@aa:8) addressing mode to specify an operand, and register direct (BSET, Rev.3.00 Mar. 26, 2007 Page 41 of 682 REJ09B0353-0300 Section 2 CPU BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.11 Addressing Modes No. 1 2 3 4 5 6 7 8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @ERn @(d:16, ERn)/@d:24, ERn) @Ern+ @-ERn @aa:8/@aa:16/@aa:24 #xx:8/#xx:16/#xx:32 @(d:8, PC)/@(d:16, PC) @@aa:8 1. Register Direct--Rn The register field of the instruction code specifies an 8-, 16-, or 32-bit register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. 2. Register Indirect--@ERn The register field of the instruction code specifies an address register (ERn), the lower 24 bits of which contain the address of the operand. 3. Register Indirect with Displacement--@(d:16, ERn) or @(d:24, ERn) A 16-bit or 24-bit displacement contained in the instruction code is added to the contents of an address register (ERn) specified by the register field of the instruction, and the lower 24 bits of the sum specify the address of a memory operand. A 16-bit displacement is sign-extended when added. Rev.3.00 Mar. 26, 2007 Page 42 of 682 REJ09B0353-0300 Section 2 CPU 4. Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents (32 bits) and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result become the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For word or longword access, the resulting register value should be even. 5. Absolute Address--@aa:8, @aa:16, or @aa:24 The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), or 24 bits long (@aa:24). For an 8-bit absolute address, the upper 16 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 8 bits are a sign extension. A 24-bit absolute address can access the entire address space. Table 2.12 indicates the accessible address ranges. Table 2.12 Absolute Address Access Ranges Absolute Address 8 bits (@aa:8) 1-Mbyte Modes H'FFF00 to H'FFFFF (1,048,320 to 1,048,575) 16-Mbyte Modes H'FFFF00 to H'FFFFFF (16,776,960 to 16,777,215) H'000000 to H'007FFF, H'FF8000 to H'FFFFFF (0 to 32,767, 16,744,448 to 16,777,215) H'000000 to H'FFFFFF (0 to 16,777,215) 16 bits (@aa:16) H'00000 to H'07FFF, H'F8000 to H'FFFFF (0 to 32,767, 1,015,808 to 1,048,575) 24 bits (@aa:24) H'00000 to H'FFFFF (0 to 1,048,575) Rev.3.00 Mar. 26, 2007 Page 43 of 682 REJ09B0353-0300 Section 2 CPU 6. Immediate--#xx:8, #xx:16, or #xx:32 The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The instruction codes of the ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. The instruction codes of some bit manipulation instructions contain 3-bit immediate data specifying a bit number. The TRAPA instruction code contains 2-bit immediate data specifying a vector address. 7. Program-Counter Relative--@(d:8, PC) or @(d:16, PC) This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign-extended to 24 bits and added to the 24-bit PC contents to generate a 24-bit branch address. The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. 8. Memory Indirect--@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access. The first byte of the memory operand is ignored, generating a 24-bit branch address. See figure 2.10. The upper bits of the 8-bit absolute address are assumed to be 0 (H'0000), so the address range is 0 to 255 (H'000000 to H'0000FF). Note that the first part of this range is also the exception vector area. For further details see section 5, Interrupt Controller. Specified by @aa:8 Reserved Branch address Figure 2.10 Memory-Indirect Branch Address Specification Rev.3.00 Mar. 26, 2007 Page 44 of 682 REJ09B0353-0300 Section 2 CPU When a word-size or longword-size memory operand is specified, or when a branch address is specified, if the specified memory address is odd, the least significant bit is regarded as 0. The accessed data or instruction code therefore begins at the preceding address. See section 2.5.2, Memory Data Formats. 2.7.2 Effective Address Calculation Table 2.13 explains how an effective address is calculated in each addressing mode. In the 1-Mbyte operating modes the upper 4 bits of the calculated address are ignored in order to generate a 20-bit effective address. Rev.3.00 Mar. 26, 2007 Page 45 of 682 REJ09B0353-0300 No. Operand is general register contents 31 23 General register contents 0 0 Addressing Mode and Instruction Format Effective Address Calculation Effective Address 1 Register direct (Rn) Section 2 CPU op rm rn 2 Register indirect (@ERn) op 31 General register contents 23 0 r 3 Register indirect with displacement @(d:16, ERn)/@(d:24, ERn) Rev.3.00 Mar. 26, 2007 Page 46 of 682 REJ09B0353-0300 0 disp Sign extension disp 31 General register contents 0 23 0 1, 2, or 4 31 General register contents 0 23 1, 2, or 4 1 for a byte operand, 2 for a word operand, 4 for a longword operand 0 Table 2.13 Effective Address Calculation op r 4 Register indirect with post-increment or pre-decrement Register indirect with post-increment @ERn+ op r Register indirect with pre-decrement @ERn op r No. 23 H'FFFF 87 Addressing Mode and Instruction Format Effective Address Calculation Effective Address 0 5 abs 23 Sign extension Absolute address @aa:8 op 16 15 0 @aa:16 abs 23 op 0 @aa:24 op abs Operand is immediate data 6 IMM Immediate #xx:8, #xx:16, or #xx:32 op 7 Program-counter relative @(d:8, PC) or @(d:16, PC) 23 PC contents 0 23 Sign extension 0 disp Rev.3.00 Mar. 26, 2007 Page 47 of 682 REJ09B0353-0300 disp op Section 2 CPU No. Addressing Mode and Instruction Format Effective Address Calculation Effective Address Section 2 CPU 8 Memory indirect @@aa:8 Normal mode abs 23 H'0000 15 0 Memory contents abs 23 16 15 H'00 0 87 0 Rev.3.00 Mar. 26, 2007 Page 48 of 682 REJ09B0353-0300 abs 23 H'0000 31 Memory contents 87 abs 0 23 0 0 op Advanced mode op Legend: r, rm, rn: op: disp: IMM: abs: Register field Operation field Displacement Immediate data Absolute address Section 2 CPU 2.8 2.8.1 Processing States Overview The H8/300H CPU has four processing states: the program execution state, exception-handling state, power-down state, and reset state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 classifies the processing states. Figure 2.13 indicates the state transitions. Processing states Program execution state The CPU executes program instructions in sequence Exception-handling state A transient state in which the CPU executes a hardware sequence (saving PC and CCR, fetching a vector, etc.) in response to a reset, interrupt, or other exception Reset state The CPU and all on-chip supporting modules are initialized and halted Power-down state The CPU is halted to conserve power Sleep mode Software standby mode Hardware standby mode Figure 2.11 Processing States 2.8.2 Program Execution State In this state the CPU executes program instructions in normal sequence. Rev.3.00 Mar. 26, 2007 Page 49 of 682 REJ09B0353-0300 Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, or trap instruction. The CPU fetches a starting address from the exception vector table and branches to that address. In interrupt and trap exception handling the CPU references the stack pointer (ER7) and saves the program counter and condition code register. Types of Exception Handling and Their Priority: Exception handling is performed for resets, interrupts, and trap instructions. Table 2.14 indicates the types of exception handling and their priority. Trap instruction exceptions are accepted at all times in the program execution state. Table 2.14 Exception Handling Types and Priority Priority High Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately when RES changes from low to high When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Interrupt End of instruction execution or end of exception handling* Trap instruction Low Note: * When TRAPA instruction Exception handling starts when is executed a trap (TRAPA) instruction is executed Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. Figure 2.12 classifies the exception sources. For further details about exception sources, vector numbers, and vector addresses, see section 4, Exception Handling, and section 5, Interrupt Controller. Rev.3.00 Mar. 26, 2007 Page 50 of 682 REJ09B0353-0300 Section 2 CPU Reset External interrupts Exception sources Interrupt Internal interrupts (from on-chip supporting modules) Trap instruction Figure 2.12 Classification of Exception Sources Program execution state SLEEP instruction with SSBY = 0 End of exception handling Exception Sleep mode Interrupt NMI, IRQ 0 , IRQ 1, or IRQ 2 interrupt SLEEP instruction with SSBY = 1 Exception-handling state Software standby mode RES = high STBY = high, RES = low Reset state*1 Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2.13 State Transitions 2.8.4 Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception handling starts the CPU fetches a start address from the exception vector table and starts program execution from that address. All interrupts, Rev.3.00 Mar. 26, 2007 Page 51 of 682 REJ09B0353-0300 Section 2 CPU including NMI, are disabled during the reset exception-handling sequence and immediately after it ends. Interrupt Exception Handling and Trap Instruction Exception Handling: When these exception-handling sequences begin, the CPU references the stack pointer (ER7) and pushes the program counter and condition code register on the stack. Next, if the UE bit in the system control register (SYSCR) is set to 1, the CPU sets this set to 1, the CPU sets the I bit in the condition code register to 1. If the UE bit is cleared to 0, the CPU sets both the I bit and the UI bit in the condition code register to 1. Then the CPU fetches a start address from the exception vector table and execution branches to that address. Figure 2.14 shows the stack after the exception-handling sequence. SP4 SP3 SP2 SP1 SP (ER7) Stack area SP (ER7) SP+1 SP+2 SP+3 SP+4 CCR PC Even address Before exception handling starts Legend: CCR: Condition code register SP: Stack pointer Pushed on stack After exception handling ends Notes: 1. PC is the address of the first instruction executed after the return from the exception-handling routine. 2. Registers must be saved and restored by word access or longword access, starting at an even address. Figure 2.14 Stack Structure after Exception Handling Rev.3.00 Mar. 26, 2007 Page 52 of 682 REJ09B0353-0300 Section 2 CPU 2.8.5 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The I bit in the condition code register is set to 1 by a reset. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details see section 10, Watchdog Timer. 2.8.6 Power-Down State In the power-down state the CPU stops operating to conserve power. There are three modes: sleep mode, software standby mode, and hardware standby mode. Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the SSBY bit is cleared to 0 in the system control register (SYSCR). CPU operations stop immediately after execution of the SLEEP instruction, but the contents of CPU registers are retained. Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit is set to 1 in SYSCR. The CPU and clock halt and all on-chip supporting modules stop operating. The on-chip supporting modules are reset, but as long as a specified voltage is supplied the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. Hardware Standby Mode: A transition to hardware standby mode is made when the STBY input goes low. As in software standby mode, the CPU and clock halt and the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. For further information see section 17, Power-Down State. Rev.3.00 Mar. 26, 2007 Page 53 of 682 REJ09B0353-0300 Section 2 CPU 2.9 2.9.1 Basic Operational Timing Overview The H8/300H CPU operates according to the system clock (). The interval from one rise of the system clock to the next rise is referred to as a "state." A memory cycle or bus cycle consists of two or three states. The CPU uses different methods to access on-chip memory, the on-chip supporting modules, and the external address space. Access to the external address space can be controlled by the bus controller. 2.9.2 On-Chip Memory Access Timing On-chip memory is accessed in two states. The data bus is 16 bits wide, permitting both byte and word access. Figure 2.15 shows the on-chip memory access cycle. Figure 2.16 indicates the pin states. Bus cycle T1 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Write data Read data Address T2 state Figure 2.15 On-Chip Memory Access Cycle Rev.3.00 Mar. 26, 2007 Page 54 of 682 REJ09B0353-0300 Section 2 CPU T1 Address bus AS , RD, WR Address T2 High High impedance D7 to D0 Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide, depending on the register being accessed. Figure 2.17 shows the on-chip supporting module access timing. Figure 2.18 indicates the pin states. Bus cycle T1 state Internal address bus Internal read signal Internal data bus Address T2 state T3 state Read access Read data Internal write signal Write access Internal data bus Write data Figure 2.17 Access Cycle for On-Chip Supporting Modules Rev.3.00 Mar. 26, 2007 Page 55 of 682 REJ09B0353-0300 Section 2 CPU T1 Address bus AS , RD, WR T2 T3 Address High High impedance D7 to D0 Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas 0 to 7). Bus-controller settings determine whether each area accessed in two or three states. For details see section 6, Bus Controller. Rev.3.00 Mar. 26, 2007 Page 56 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 3.1.1 Overview Operating Mode Selection The H8/3039 Group has five operating modes (modes 1, 3, 5 to7) that are selected by the mode pins (MD2 to MD0) as indicated in table 3.1. The input at these pins determines expanded mode or single-chip mode. Table 3.1 Operating Mode Selection Mode Pins Operating Mode MD2 -- Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Mode 6 Mode 7 0 0 0 0 1 1 1 1 MD1 0 0 1 1 0 0 1 1 MD0 0 1 0 1 0 1 0 1 Address Space -- Expanded mode -- Expanded mode -- Expanded mode Single-chip normal mode Description Initial Bus On-Chip On-Chip 1 Mode* ROM RAM -- 8 bits -- 8 bits -- 8 bits -- -- Disabled -- Disabled -- Enabled Enabled Enabled -- Enabled* -- Enabled* -- Enabled* Enabled* Enabled* 1 2 2 1 1 Single-chip advanced mode -- Notes: 1. If the RAM enable bit (RAME) in the system control register (SYSCR) is cleared to 0, these addresses become external addresses. 2. In mode 6 and 7, clearing bit RAME in SYSCR to 0 and reading the on-chip RAM always return H'FF, and write access is ignored. For details, see section 14.3, Operation. For the address space size there are three choices: 64 kbytes, 1 Mbyte, or 16 Mbytes. Modes 1 and 3 are on-chip ROM disable expanded modes capable of accessing external memory and peripheral devices. Mode 1 supports a maximum address space of 1 Mbyte. Mode 3 supports a maximum address space of 16 Mbytes. Rev.3.00 Mar. 26, 2007 Page 57 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes Mode 5 is externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 1 Mbyte. Modes 6 and 7 are single-chip modes that operate using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 6 is a normal mode with 64-kbyte address space. Mode 7 is an advanced mode with a maximum address space of 1 Mbyte. The H8/3039 Group can be used only in modes 1, 3, or 5 to 7. The inputs at the mode pins must select one of these seven modes. The inputs at the mode pins must not be changed during operation. 3.1.2 Register Configuration The H8/3039 Group has a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR). Table 3.2 summarizes these registers. Table 3.2 Address* H'FFF1 H'FFF2 Note: * Registers Name Mode control register System control register Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'0B The lower 16 bits of the address are indicated. Rev.3.00 Mar. 26, 2007 Page 58 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes 3.2 Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3039 Group. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Reserved bits Mode select 2 to 0 Bits indicating the current operating mode Note: Determined by pins MD2 to MD 0 . Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bits 5 to 3--Reserved: These bits cannot be modified and are always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the logic levels at pins MD2 to MD0 (the current operating mode). MDS2 to MDS0 correspond to MD2 to MD0. MDS1 and MDS0 are read-only bits. The mode pin (MD2 to MD0) levels are latched when MDCR is read. Rev.3.00 Mar. 26, 2007 Page 59 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes 3.3 System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3039 Group. Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 -- 1 -- 0 RAME 1 R/W RAM enable Enables or disables on-chip RAM Reserved bit NMI edge select Selects the valid edge of the NMI input User bit enable Selects whether to use UI bit in CCR as a user bit or an interrupt mask bit Standby timer select 2 to 0 These bits select the waiting time at recovery from software standby mode Software standby Enables transition to software standby mode Bit 7--Software Standby (SSBY): Enables transition to software standby mode. (For further information about software standby mode see section 17, Power-Down State.) When software standby mode is exited by an external interrupt, this bit remains set to 1. To clear this bit, write 0. Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value) Bits 6 to 4--Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by an external interrupt. Set these bits so that the waiting time will be at Rev.3.00 Mar. 26, 2007 Page 60 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes least 7 ms at the system clock rate. For further information about waiting time selection, see section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode. Bit 6 STS2 0 0 0 0 1 1 1 Bit 5 STS1 0 0 1 1 0 0 1 Bit 4 STS0 0 1 0 1 0 1 -- Description Waiting time = 8,192 states Waiting time = 16,384 states Waiting time = 32,768 states Waiting time = 65,536 states Waiting time = 131,072 states Waiting time = 1,024 states Illegal setting (Initial value) Bit 3--User Bit Enable (UE): Selects whether to use the UI bit in the condition code register as a user bit or an interrupt mask bit. Bit 3 UE 0 1 Description UI bit in CCR is used as an interrupt mask bit UI bit in CCR is used as a user bit (Initial value) Bit 2--NMI Edge Select (NMIEG): Selects the valid edge of the NMI input. Bit 2 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI An interrupt is requested at the rising edge of NMI (Initial value) Bit 1--Reserved: This bit cannot be modified and is always read as 1. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized by the rising edge of the RES signal. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 61 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes 3.4 3.4.1 Operating Mode Descriptions Mode 1 Ports 1, 2, and 5 function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. 3.4.2 Mode 3 Ports 1, 2, and 5 and part of port A function as address pins A23 to A0, permitting access to a maximum 16-Mbyte address space. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. A23 to A21 are valid when 0 is written in bits 7 to 5 of the bus release control register (BRCR). (In this mode A20 is always used for address output.) 3.4.3 Mode 5 Ports 1, 2, and 5 can function as address pins A19 to A0, permitting access to a maximum 1-Mbyte address space, but following a reset they are input ports. To use ports 1, 2, and 5 as an address bus, the corresponding bits in their data direction registers (P1DDR, P2DDR, and P5DDR) must be set to 1. The address bus width can be selected freely by setting DDR of ports 1, 2, and 5. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. 3.4.4 Mode 6 This mode operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Mode 6 is a normal mode with 64-kbyte address space. 3.4.5 Mode 7 This mode is an advanced mode with a 1-Mbyte address space which operates using the on-chip ROM, RAM, and registers. All I/O ports are available. Note: The H8/3039 Group cannot be used in mode 2 and 4. Rev.3.00 Mar. 26, 2007 Page 62 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes 3.5 Pin Functions in Each Operating Mode The pin functions of ports 1 to 3, port 5 and port A vary depending on the operating mode. Table 3.3 indicates their functions in each operating mode. Table 3.3 Port Port 1 Port 2 Port 3 Port 5 Port A Pin Functions in Each Mode Mode 2* -- -- -- -- 1 Mode 1 A7 to A0 A15 to A8 D7 to D0 A19 to A16 Mode 3 A7 to A0 A15 to A8 D7 to D0 A19 to A16 3 Mode 4* -- -- -- -- 1 Mode 5 P17 to P10* D7 to D0 P53 to P50* PA7 to PA4 2 2 2 Mode 6 P17 to P10 P27 to P20 P37 to P30 P53 to P50 Mode 7 P17 to P10 P27 to P20 P37 to P30 P53 to P50 P27 to P20* PA7 to PA4 -- PA6 to PA4* , A20 -- PA7 to PA4 PA7 to PA4 Notes: 1. H8/3039 Group cannot be used in these modes. 2. Initial state. These pins become address output pins when the corresponding bits in the data direction registers (P1DDR, P2DDR, P5DDR) are set to 1. 3. Initial state A20 is always an address output pin. PA6 to PA4 are switched over to A23 to A21 output by writing 0 in bits 7 to 5 of ADRCR. 3.6 Memory Map in Each Operating Mode Figure 3.1 shows a memory map of the H8/3039. Figure 3.2 shows a memory map of the H8/3038. Figure 3.3 shows a memory map of the H8/3037. Figure 3.4 shows a memory map of the H8/3036. The address space is divided into eight areas. Modes 1, 3 and 5 are the 8-bit bus mode. The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte modes (modes 1, 5, and 7) and 16-Mbyte mode (mode 3), and 64-kbyte mode (mode 6). The address range specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also differs. Rev.3.00 Mar. 26, 2007 Page 63 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes Mode 1 (1-Mbyte expanded modes with on-chip ROM disabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 3 (16-Mbyte expanded modes with on-chip ROM disabled) Vector area 8-bit memory-indirect branch addresses 16-bit absolute addresses (first half) H'00000 Vector area H'000000 H'000FF H'0000FF H'07FFF H'007FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'7FFFFF H'800000 H'9FFFFF H'A00000 16-bit absolute addresses (second half) Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address space Area 3 Area 4 H'F8000 H'FEF0F H'FEF10 H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF Area 5 H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 Area 7 External address space On-chip I/O registers 8-bit absolute addresses On-chip RAM* H'FF8000 16-bit absolute addresses (second half) H'FFEF0F H'FFEF10 H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C H'FFFFFF External address space On-chip I/O registers Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1 H8/3039 Memory Map in Each Operating Mode (1) Rev.3.00 Mar. 26, 2007 Page 64 of 682 REJ09B0353-0300 8-bit absolute addresses On-chip RAM* Section 3 MCU Operating Modes Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 6 (single-chip normal mode) 8-bit memory-indirect branch addresses Mode 7 (single-chip advanced mode) 8-bit memory-indirect branch addresses H'00000 Vector area H'0000 Vector area H'00000 Vector area H'000FF On-chip ROM H'07FFF H'00FF H'000FF On-chip ROM H'07FFF H'1FFFF On-chip ROM H'F70F H'F710 H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 Area 0 Area 1 F'FF00 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'FF1C H'FFFF F'FF0F On-chip I/O registers 8-bit absolute addresses On-chip RAM H'F8000 16-bit absolute addresses (second half) H'F8000 H'FEF10 H'FFF00 H'FFF0F 8-bit absolute addresses 16-bit absolute addresses (second half) H'FEF0F H'FEF10 H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF External address space On-chip I/O registers 8-bit absolute addresses On-chip RAM* On-chip RAM H'FFF1C H'FFFFF On-chip I/O registers Note: * External addresses can be accessed by disabling on-chip RAM. Figure 3.1 H8/3039 Memory Map in Each Operating Mode (2) Rev.3.00 Mar. 26, 2007 Page 65 of 682 REJ09B0353-0300 16-bit absolute addresses (first half) Section 3 MCU Operating Modes Mode 1 (1-Mbyte expanded modes with on-chip ROM disabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 3 (16-Mbyte expanded modes with on-chip ROM disabled) Vector area 8-bit memory-indirect branch addresses 16-bit absolute addresses (first half) H'00000 Vector area H'000000 H'000FF H'0000FF H'07FFF H'007FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'7FFFFF H'800000 H'9FFFFF H'A00000 16-bit absolute addresses (second half) Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address space Area 3 Area 4 H'F8000 H'FEF10 H'FF70F H'FF710 H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF Reserved*1 8-bit absolute addresses Area 5 H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 Area 7 On-chip RAM*2 External address space On-chip I/O registers H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C H'FFFFFF External address space On-chip I/O registers Notes: 1. Do not access the reserved area. 2. External addresses can be accessed by disabling on-chip RAM. Figure 3.2 H8/3038 Memory Map in Each Operating Mode (1) Rev.3.00 Mar. 26, 2007 Page 66 of 682 REJ09B0353-0300 8-bit absolute addresses On-chip RAM*2 16-bit absolute addresses (second half) H'FF8000 H'FFEF10 H'FFF70F H'FFF710 Reserved*1 Section 3 MCU Operating Modes Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 6 (single-chip normal mode) 8-bit memory-indirect branch addresses Mode 7 (single-chip advanced mode) 8-bit memory-indirect branch addresses 16-bit absolute addresses (first half) H'00000 Vector area H'0000 Vector area H'00000 Vector area H'000FF On-chip ROM H'07FFF H'08000 H'0FFFF Reserved*1 H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'00FF On-chip ROM H'F70F H'F710 On-chip RAM H'FF00 H'FF0F H'FF1C H'FFFF On-chip I/O registers H'000FF On-chip ROM H'07FFF H'0FFFF Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 8-bit absolute addresses H'F8000 H'FF710 16-bit absolute addresses (second half) 16-bit absolute addresses (second half) H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF External address space On-chip I/O registers 8-bit absolute addresses On-chip RAM*2 H'FFF00 H'FFF0F H'FFF1C H'FFFFF On-chip I/O registers Notes: 1. Do not access the reserved area. 2. External addresses can be accessed by disabling on-chip RAM. Figure 3.2 H8/3038 Memory Map in Each Operating Mode (2) Rev.3.00 Mar. 26, 2007 Page 67 of 682 REJ09B0353-0300 8-bit absolute addresses H'F8000 H'FEF10 H'FF70F H'FF710 Reserved*1 On-chip RAM Section 3 MCU Operating Modes Mode 1 (1-Mbyte expanded modes with on-chip ROM disabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 3 (16-Mbyte expanded modes with on-chip ROM disabled) Vector area 8-bit memory-indirect branch addresses 16-bit absolute addresses (first half) H'00000 Vector area H'000000 H'000FF H'0000FF H'07FFF H'007FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'7FFFFF H'800000 H'9FFFFF H'A00000 16-bit absolute addresses (second half) Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address space Area 3 Area 4 H'F8000 H'FEF10 H'FFB0F H'FFB10 H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF Reserved*1 8-bit absolute addresses Area 5 H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 Area 7 On-chip RAM*2 External address space On-chip I/O registers H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C H'FFFFFF External address space On-chip I/O registers Notes: 1. Do not access the reserved area. 2. External addresses can be accessed by disabling on-chip RAM. Figure 3.3 H8/3037 Memory Map in Each Operating Mode (1) Rev.3.00 Mar. 26, 2007 Page 68 of 682 REJ09B0353-0300 8-bit absolute addresses On-chip RAM*2 16-bit absolute addresses (second half) H'FF8000 H'FFEF10 H'FFFB0F H'FFFB10 Reserved*1 Section 3 MCU Operating Modes Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 6 (single-chip normal mode) 8-bit memory-indirect branch addresses Mode 7 (single-chip advanced mode) 8-bit memory-indirect branch addresses 16-bit absolute addresses (first half) H'00000 Vector area H'0000 Vector area H'00000 Vector area H'000FF On-chip ROM H'07FFF H'08000 Reserved*1 H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'00FF On-chip ROM H'7FFF H'000FF On-chip ROM H'07FFF H'FB10 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'F8000 H'FFB10 16-bit absolute addresses (second half) 16-bit absolute addresses (second half) H'FF00 H'FF0F H'FF1C H'FFFF On-chip I/O registers H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF External address space On-chip I/O registers 8-bit absolute addresses On-chip RAM*2 H'FFF00 H'FFF0F H'FFF1C H'FFFFF On-chip I/O registers Notes: 1. Do not access the reserved area. 2. External addresses can be accessed by disabling on-chip RAM. Figure 3.3 H8/3037 Memory Map in Each Operating Mode (2) Rev.3.00 Mar. 26, 2007 Page 69 of 682 REJ09B0353-0300 8-bit absolute addresses H'F8000 H'FEF10 H'FFB0F H'FFB10 Reserved*1 8-bit absolute addresses On-chip RAM On-chip RAM Section 3 MCU Operating Modes Mode 1 (1-Mbyte expanded modes with on-chip ROM disabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 3 (16-Mbyte expanded modes with on-chip ROM disabled) Vector area 8-bit memory-indirect branch addresses 16-bit absolute addresses (first half) H'00000 Vector area H'000000 H'000FF H'0000FF H'07FFF H'007FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 H'7FFFFF H'800000 H'9FFFFF H'A00000 16-bit absolute addresses (second half) Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address space Area 3 Area 4 H'F8000 H'FEF10 H'FFD0F H'FFD10 H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF Reserved*1 8-bit absolute addresses Area 5 H'BFFFFF H'C00000 Area 6 H'DFFFFF H'E00000 Area 7 On-chip RAM*2 External address space On-chip I/O registers H'FFFF00 H'FFFF0F H'FFFF10 H'FFFF1B H'FFFF1C H'FFFFFF External address space On-chip I/O registers Notes: 1. Do not access the reserved area. 2. External addresses can be accessed by disabling on-chip RAM. Figure 3.4 H8/3036 Memory Map in Each Operating Mode (1) Rev.3.00 Mar. 26, 2007 Page 70 of 682 REJ09B0353-0300 8-bit absolute addresses On-chip RAM*2 16-bit absolute addresses (second half) H'FF8000 H'FFEF10 H'FFFD0F H'FFFD10 Reserved*1 Section 3 MCU Operating Modes Mode 5 (1-Mbyte expanded mode with on-chip ROM enabled) 16-bit absolute addresses (first half) 8-bit memory-indirect branch addresses Mode 6 (single-chip normal mode) 8-bit memory-indirect branch addresses Mode 7 (single-chip advanced mode) 8-bit memory-indirect branch addresses 16-bit absolute addresses (first half) H'00000 Vector area H'0000 Vector area H'00000 Vector area H'000FF On-chip ROM H'03FFF H'07FFF Reserved*1 H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'00FF On-chip ROM H'3FFF H'000FF On-chip ROM H'03FFF H'FD10 8-bit absolute addresses Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 F'FF00 F'FF0F H'FF1C H'FFFF On-chip RAM On-chip I/O registers H'F8000 H'FFD10 16-bit absolute addresses (second half) 16-bit absolute addresses (second half) H'FFF00 H'FFF0F H'FFF10 H'FFF1B H'FFF1C H'FFFFF External address space On-chip I/O registers 8-bit absolute addresses On-chip RAM*2 H'FFF00 H'FFF0F H'FFF1C H'FFFFF On-chip I/O registers Notes: 1. Do not access the reserved area. 2. External addresses can be accessed by disabling on-chip RAM. Figure 3.4 H8/3036 Memory Map in Each Operating Mode (2) Rev.3.00 Mar. 26, 2007 Page 71 of 682 REJ09B0353-0300 8-bit absolute addresses H'F8000 H'FEF10 H'FFD0F H'FFD10 Reserved*1 On-chip RAM Section 3 MCU Operating Modes 3.7 Restrictions on Use of Mode 6 In mode 6 (single-chip normal mode), on-chip ROM area data is undefined if address H'10000 or above (64 kbytes or above) is accessed, and therefore instruction code fetch and data read operations may not always be performed normally. However, there is no problem with address H'10000 and above if the lower 16-bit address is an on-chip RAM (H'F710 to H'FF0F) or internal I/O register (H'FF1C to H'FFFF) address. Table 3.4 shows the restrictions concerning each addressing mode. Table 3.4 Access Restrictions in Mode 6 (Single-Chip Normal Mode) Conditions Addressing Mode Register direct (Rn) Register indirect (@ERn) Restricted Item Contents of ERn Address Range H'00010000 or above, with lower 16 bits in range H'0000 to H'F710 Operation No problem Read data is undefined. Writes are invalid. Restriction Set upper 16 bits of ERn to H'0000; or, write same data as in H'00000-H'0FFFF to H'10000-H'1FFFF in on-chip ROM. Register indirect with displacement (@(d:16,ERn), @(d:16,ERn)) Register indirect with post-increment (@ERn+) Register indirect with pre-decrement (@ERn-) Absolute address (@aa:8) Absolute address (@aa:16) Value of ERn contents plus displacement Value of ERn contents incremented (or decremented) by 1, 2, or 4 Value of @aa sign-extended to 24 bits H'010000 or above, with lower 16 bits in range H'0000 to H'F710 Do not specify H'8000 or above as absolute address; or, write same data as in H'00000- H'0FFFF to H'10000- H'1FFFF in on-chip ROM. No problem Read data is undefined. Writes are invalid. Rev.3.00 Mar. 26, 2007 Page 72 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes Conditions Addressing Mode Absolute address (@aa:24) Restricted Item Value of @aa Address Range H'010000 or above, with lower 16 bits in range H'0000 to H'F710 Operation Read data is undefined. Writes are invalid. Restriction Do not access addresses in range shown under conditions; or, write same data as in H'00000-H'0FFFF to H'10000-H'1FFFF in on-chip ROM. Do not access addresses in range shown under conditions; or, write same data as in H'00000-H'0FFFF to H'10000-H'1FFFF in on-chip ROM. Immediate Program-counter relative (@(d:8,PC), @(d:16,PC)) Value of PC plus displacement H'010000 or above, with lower 16 bits in range H'0000 to H'F710 No problem Does not operate normally since instruction code is undefined. No problem Memory indirect (@@aa:8) Rev.3.00 Mar. 26, 2007 Page 73 of 682 REJ09B0353-0300 Section 3 MCU Operating Modes Rev.3.00 Mar. 26, 2007 Page 74 of 682 REJ09B0353-0300 Section 4 Exception Handling Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in priority order. Trap instruction exceptions are accepted at all times in the program execution state. Table 4.1 Priority High Exception Types and Priority Exception Type Reset Interrupt Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin Interrupt requests are handled when execution of the current instruction or handling of the current exception is completed Started by execution of a trap instruction (TRAPA) Low Trap instruction (TRAPA) 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows. 1. The program counter (PC) and condition code register (CCR) are pushed onto the stack. 2. The CCR interrupt mask bit is set to 1. 3. A vector address corresponding to the exception source is generated, and program execution starts from the address indicated in the vector address. For a reset exception, steps 2 and 3 above are carried out. Rev.3.00 Mar. 26, 2007 Page 75 of 682 REJ09B0353-0300 Section 4 Exception Handling 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. * Reset External interrupts: NMI, IRQ0, IRQ1, IRQ4, IRQ5 Exception sources * Interrupts Internal interrupts: 25 interrupts from on-chip supporting modules * Trap instruction Figure 4.1 Exception Sources Rev.3.00 Mar. 26, 2007 Page 76 of 682 REJ09B0353-0300 Section 4 Exception Handling Table 4.2 Exception Vector Table Vector Address* 1 Exception Source Reset Reserved for system use Vector Number 0 1 2 3 4 5 6 Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 to H'0078 to H'0079 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 to H'00F0 to H'00F3 External interrupt (NMI) Trap instruction (4 sources) 7 8 9 10 11 External interrupt IRQ0 IRQ1 12 13 14 15 Reserved for system use External interrupt IRQ4 IRQ5 16 17 18 19 Reserved for system use 2 Internal interrupts* 20 to 60 Notes: 1. Lower 16 bits of the address. 2. For the internal interrupt vectors, see section 5.3.3, Interrupt Vector Table. Rev.3.00 Mar. 26, 2007 Page 77 of 682 REJ09B0353-0300 Section 4 Exception Handling 4.2 4.2.1 Reset Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the H8/3039 Group enters the reset state. A reset initializes the internal state of the CPU and the registers of the on-chip supporting modules. Reset exception handling begins when the RES pin changes from low to high. The chip can also be reset by overflow of the watchdog timer. For details see section 10, Watchdog Timer. 4.2.2 Reset Sequence The H8/3039 Group enters the reset state when the RES pin goes low. To ensure that the chip is reset, hold the RES pin low for at least 20 ms at power-up. To reset the chip during operation, hold the RES pin low for at least 10 system clock () cycles. When using the flash memory version, hold at "Low" level for a least 1usec. See appendix D.2, Pin States at Reset, for the states of the pins in the reset state. When the RES pin goes high after being held low for the necessary time, the H8/3039 Group chip starts reset exception handling as follows. * The internal state of the CPU and the registers of the on-chip supporting modules are initialized, and the I bit is set to 1 in CCR. * The contents of the reset vector address (H'0000 to H'0003 in advanced mode) are read, and program execution starts from the address indicated in the vector address. Figure 4.2 shows the reset sequence in modes 5 and 7. Rev.3.00 Mar. 26, 2007 Page 78 of 682 REJ09B0353-0300 Vector fetch Internal processing Prefetch of first program instruction RES Internal address bus (1) (3) (5) Internal read signal Internal write signal (2) (4) (6) Figure 4.2 Reset Sequence (Modes 5 and 7) Internal data bus (16-bit width) Section 4 Exception Handling Rev.3.00 Mar. 26, 2007 Page 79 of 682 REJ09B0353-0300 (1), (3) (2), (4) (5) (6) Address of reset vector: (1) = H'000000, (3) = H'000002 Start address (contents of reset vector) Start address First instruction of program Section 4 Exception Handling 4.2.3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. The first instruction of the program is always executed immediately after the reset state ends. This instruction should initialize the stack pointer (example: MOV.L #xx:32, SP). 4.3 Interrupts Interrupt exception handling can be requested by five external sources (NMI, IRQ0, IRQ1, IRQ4, IRQ5) and 25 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting modules that can request interrupts are the watchdog timer (WDT), 16-bit integrated timer unit (ITU), serial communication interface (SCI), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt and is always accepted. Interrupts are controlled by the interrupt controller. The interrupt controller can assign interrupts other than NMI to two priority levels, and arbitrate between simultaneous interrupts. Interrupt priorities are assigned in interrupt priority registers A and B (IPRA and IPRB) in the interrupt controller. For details on interrupts see section 5, Interrupt Controller. NMI (1) IRQ0, IRQ1, IRQ4, IRQ5 (4) WDT* (1) ITU (15) SCI (8) A/D converter (1) External interrupts Interrupts Internal interrupts Notes: Numbers in parentheses are the number of interrupt sources. * When the watchdog timer is used as an interval timer, it generates an interrupt request at every counter overflow. Figure 4.3 Interrupt Sources and Number of Interrupts Rev.3.00 Mar. 26, 2007 Page 80 of 682 REJ09B0353-0300 Section 4 Exception Handling 4.4 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set to 1 in the system control register (SYSCR), the exception handling sequence sets the I bit to 1 in CCR. If the UE bit is 0, the I and UI bits are both set to 1. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, which is specified in the instruction code. 4.5 Stack Status after Exception Handling Figure 4.4 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP-4 SP-3 SP-2 SP-1 SP (ER7) Stack area SP (ER7) SP+1 SP+2 SP+3 SP+4 CCR PC E PC H PC L Even address Before exception handling Save on stack After exception handling Legend: PCE: Bits 23 to 16 of program counter (PC) PCH: Bits 15 to 8 of program counter (PC) PCL: Bits 7 to 0 of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1. PC indicates the address of the first instruction that will be executed after return. 2. Saving and restoring of registers must be conducted at even addresses in word-size or longword-size units. Figure 4.4 Stack after Completion of Exception Handling (Advanced Mode) Rev.3.00 Mar. 26, 2007 Page 81 of 682 REJ09B0353-0300 Section 4 Exception Handling 4.6 Notes on Stack Usage When accessing word data or longword data, the H8/3039 Group regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn POP.L ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4.5 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L H'FFEFA H'FFEFB PC H'FFEFC H'FFEFD H'FFEFF SP TRAPA instruction executed MOV. B R1L, @-ER7 SP set to H'FFEFF Legend: CCR: PC: R1L: SP: Condition code register Program counter General register R1L Stack pointer Data saved above SP CCR contents lost Note: The diagram illustrates modes 1, 3, and 5. Figure 4.5 Operation when SP Value is Odd Rev.3.00 Mar. 26, 2007 Page 82 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The interrupt controller has the following features: * Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt priority registers A and B (IPRA and IPRB). * Three-level masking by the I and UI bits in the CPU condition code register (CCR) * Independent vector addresses All interrupts are independently vectored; the interrupt service routine does not have to identify the interrupt source. * Five external interrupt pins NMI has the highest priority and is always accepted; either the rising or falling edge can be selected. For each of IRQ0, IRQ1, IRQ4, and IRQ5, sensing of the falling edge or level sensing can be selected independently. Rev.3.00 Mar. 26, 2007 Page 83 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.1.2 Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. CPU ISCR NMI input IRQ input OVF TME . . . . . . . ADI ADIE IRQ input section ISR Priority decision logic IER IPRA, IPRB Interrupt request Vector number . . . I Interrupt controller UE SYSCR Legend: I: IER: IPRA: IPRB: ISCR: ISR: SYSCR: UE: UI: Interrupt mask bit IRQ enable register Interrupt priority register A Interrupt priority register B IRQ sense control register IRQ status register System control register User bit enable User bit/interrupt mask bit UI CCR Figure 5.1 Interrupt Controller Block Diagram Rev.3.00 Mar. 26, 2007 Page 84 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Name Nonmaskable interrupt External interrupt request 5, 4, 1, and 0 Interrupt Pins Abbreviation NMI IRQ5, IRQ4, and IRQ1, IRQ0 I/O Input Input Function Nonmaskable interrupt, rising edge or falling edge selectable Maskable interrupts, falling edge or level sensing selectable 5.1.4 Register Configuration Table 5.2 lists the registers of the interrupt controller. Table 5.2 Address* H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFF9 1 Interrupt Controller Registers Name System control register IRQ sense control register IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Abbreviation SYSCR ISCR IER ISR IPRA IPRB R/W R/W R/W R/W R/(W)* R/W R/W 2 Initial Value H'0B H'00 H'00 H'00 H'00 H'00 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written, to clear flags. Rev.3.00 Mar. 26, 2007 Page 85 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.2 5.2.1 Register Descriptions System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only bits 3 and 2 are described here. For the other bits, see section 3.3, System Control Register (SYSCR). SYSCR is initialized to H'0B by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 -- 1 -- 0 RAME 1 R/W RAM enable Reserved bit Standby timer select 2 to 0 Software standby NMI edge select Selects the NMI input edge User bit enable Selects whether to use the UI bit in CCR as a user bit or interrupt mask bit Rev.3.00 Mar. 26, 2007 Page 86 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Bit 3--User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE 0 1 Description UI bit in CCR is used as interrupt mask bit UI bit in CCR is used as user bit (Initial value) Bit 2--NMI Edge Select (NMIEG): Selects the NMI input edge. Bit 2 NMIEG 0 1 Description Interrupt is requested at falling edge of NMI input Interrupt is requested at rising edge of NMI input (Initial value) Rev.3.00 Mar. 26, 2007 Page 87 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB) IPRA and IPRB are 8-bit readable/writable registers that control interrupt priority. Interrupt Priority Register A (IPRA) IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit Initial value Read/Write 7 IPRA7 0 R/W 6 IPRA6 0 R/W 5 -- 0 R/W 4 IPRA4 0 R/W 3 IPRA3 0 R/W 2 IPRA2 0 R/W 1 IPRA1 0 R/W 0 IPRA0 0 R/W Priority level A0 Selects the priority level of ITU channel 2 interrupt requests Priority level A1 Selects the priority level of ITU channel 1 interrupt requests Priority level A2 Selects the priority level of ITU channel 0 interrupt requests Priority level A3 Selects the priority level of WDT interrupt requests Priority level A4 Selects the priority level of IRQ4 and IRQ5 interrupt requests Reserved bit Priority level A6 Selects the priority level of IRQ1 interrupt requests Priority level A7 Selects the priority level of IRQ 0 interrupt requests Rev.3.00 Mar. 26, 2007 Page 88 of 682 REJ09B0353-0300 Section 5 Interrupt Controller IPRA is initialized to H'00 by a reset and in hardware standby mode. Bit 7--Priority Level A7 (IPRA7): Selects the priority level of IRQ0 interrupt requests. Bit7 IPRA7 0 1 Description IRQ0 interrupt requests have priority level 0 (low priority) IRQ0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 6--Priority Level A6 (IPRA6): Selects the priority level of IRQ1 interrupt requests. Bit6 IPRA6 0 1 Description IRQ1 interrupt requests have priority level 0 (low priority) IRQ1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 5--Reserved bit: This bit can be written and read, but it does not affect interrupt priority. Bit 4--Priority Level A4 (IPRA4): Selects the priority level of IRQ4 and IRQ5 interrupt requests. Bit4 IPRA4 0 1 Description IRQ4, IRQ5 interrupt requests have priority level 0 (low priority) IRQ4, IRQ5 interrupt requests have priority level 1 (high priority) (Initial value) Bit 3--Priority Level A3 (IPRA3): Selects the priority level of WTD interrupt requests. Bit3 IPRA3 0 1 Description WDT interrupt requests have priority level 0 (low priority) WDT interrupt requests have priority level 1 (high priority) (Initial value) Rev.3.00 Mar. 26, 2007 Page 89 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Bit 2--Priority Level A2 (IPRA2): Selects the priority level of ITU channel 0 interrupt requests. Bit2 IPRA2 0 1 Description ITU channel 0 interrupt requests have priority level 0 (low priority) ITU channel 0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 1--Priority Level A1 (IPRA1): Selects the priority level of ITU channel 1 interrupt requests. Bit1 IPRA1 0 1 Description ITU channel 1 interrupt requests have priority level 0 (low priority) ITU channel 1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 0--Priority Level A0 (IPRA0): Selects the priority level of ITU channel 2 interrupt requests. Bit0 IPRA0 0 1 Description ITU channel 2 interrupt requests have priority level 0 (low priority) ITU channel 2 interrupt requests have priority level 1 (high priority) (Initial value) Rev.3.00 Mar. 26, 2007 Page 90 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Interrupt Priority Register B (IPRB) IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit Initial value Read/Write 7 IPRB7 0 R/W 6 IPRB6 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 IPRB3 0 R/W 2 IPRB2 0 R/W 1 IPRB1 0 R/W 0 -- 0 R/W Reserved bit Priority level B1 Selects the priority level of A/D converter interrupt request Priority level B2 Selects the priority level of SCI channel 1 interrupt requests Priority level B3 Selects the priority level of SCI channel 0 interrupt requests Reserved bits Priority level B6 Selects the priority level of ITU channel 4 interrupt requests Priority level B7 Selects the priority level of ITU channel 3 interrupt requests IPRB is initialized to H'00 by a reset and in hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 91 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Bit 7--Priority Level B7 (IPRB7): Selects the priority level of ITU channel 3 interrupt requests. Bit7 IPRB7 0 1 Description ITU channel 3 interrupt requests have priority level 0 (low priority) ITU channel 3 interrupt requests have priority level 1 (high priority) (Initial value) Bit 6--Priority Level B6 (IPRB6): Selects the priority level of ITU channel 4 interrupt requests. Bit6 IPRB6 0 1 Description ITU channel 4 interrupt requests have priority level 0 (low priority) ITU channel 4 interrupt requests have priority level 1 (high priority) (Initial value) Bits 5 and 4--Reserved: These bits cannot be modified and are always read as 0. Bit 3--Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit3 IPRB3 0 1 Description SCI channel 0 interrupt requests have priority level 0 (low priority) SCI channel 0 interrupt requests have priority level 1 (high priority) (Initial value) Bit 2--Priority Level B2 (IPRB2): Selects the priority level of SCI channel 1 interrupt requests. Bit2 IPRB2 0 1 Description SCI channel 1 interrupt requests have priority level 0 (low priority) SCI channel 1 interrupt requests have priority level 1 (high priority) (Initial value) Bit 1--Priority Level B1 (IPRB1): Selects the priority level of A/D converter interrupt requests. Bit1 IPRB1 0 1 Description A/D converter interrupt requests have priority level 0 (low priority) A/D converter interrupt requests have priority level 1 (high priority) (Initial value) Bit 0--Reserved: This bit cannot be modified and is always read as 0. Rev.3.00 Mar. 26, 2007 Page 92 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.2.3 IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ0, IRQ1, IRQ4, and IRQ5 interrupt requests. Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Reserved bits Reserved bits IRQ5 to IRQ4 flags These bits indicate IRQ5 and IRQ4 interrupt request status IRQ1, IRQ0 flags These bits indicates IRQ1 and IRQ0 interrupt request status Note: * Only 0 can be written, to clear flags. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7, 6, 3 and 2--Reserved: These bits cannot be modified and are always read as 0. Bits 5, 4, 1 and 0--IRQ5, IRQ4, IRQ1 and IRQ0 Flags (IRQ5F, IRQ4F, IRQ1F, and IRQ0F): These bits indicate the status of IRQ5, IRQ4, IRQ1, and IRQ0 interrupt requests. Bits 5, 4, 1, and 0 IRQ5F, IRQ4F, IRQ1F, and IRQ0F 0 Description [Clearing conditions] * * * (Initial value) 0 is written in IRQnF after reading the IRQnF flag when IRQnF = 1. IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. IRQnSC = 1 and IRQn interrupt exception handling is carried out. IRQnSC = 0 and IRQn input is low. IRQnSC = 1 and IRQn input changes from high to low. 1 [Setting conditions] * * Note: n = 5, 4, 1 and 0 Rev.3.00 Mar. 26, 2007 Page 93 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.2.4 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ0, IRQ1, IRQ4, and IRQ5 interrupt requests. Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W Reserved bits Reserved bits IRQ5 to IRQ4 enable These bits enable or disable IRQ5 and IRQ4 interrupts IRQ1 to IRQ0 enable These bits enable or disable IRQ1 and IRQ0 interrupts IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7, 6, 3, and 2--Reserved: These bits cannot be modified and are always read as 0. Bits 5, 4, 1, and 0--IRQ5, IRQ4, IRQ1, and IRQ0 Enable (IRQ5E, IRQ4E, IRQ1E, IRQ0E): These bits enable or disable IRQ5, IRQ4, IRQ1, IRQ0 interrupts. Bits 5, 4, 1, and 0 IRQ5E, IRQ4E, IRQ1E, and IRQ0E 0 1 Description IRQ5, IRQ4, IRQ1, IRQ0 interrupts are disabled IRQ5, IRQ4, IRQ1, IRQ0 interrupts are enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 94 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.2.5 IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ5, IRQ4, IRQ1, and IRQ0 Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 0 R/W 4 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 0 R/W 0 0 R/W IRQ5SC IRQ4SC IRQ1SC IRQ0SC Reserved bits Reserved bits IRQ5 and IRQ4 sense control These bits select level sensing or falling-edge sensing for IRQ5 and IRQ4 interrupts IRQ1 and IRQ0 sense control These bits select level sensing or falling-edge sensing for IRQ1 and IRQ0 interrupts ISCR is initialized to H'00 by a reset and in hardware standby mode. Bits 7, 6, 3, and 2--Reserved: These bits are readable/writable and do not affect selection of level sensing or falling-edge sensing. Bits 5, 4, 1, and 0--IRQ5, IRQ4, IRQ1,,and IRQ0 Sense Control (IRQ5SC, IRQ4SC, IRQ1SC, IRQ0SC): These bits selects whether interrupts IRQ5, IRQ4, IRQ1, IRQ0 are requested by level sensing of pins IRQ5, IRQ4, IRQ1, IRQ0 or by falling-edge sensing. Bits 5, 4, 1, and 0 IRQ5SC, IRQ4SC, IRQ1SC, IRQ0SC 0 1 Description Interrupts are requested when IRQ5, IRQ4, IRQ1, IRQ0 inputs are low (Initial value) Interrupts are requested by falling-edge input at IRQ5, IRQ4, IRQ1, IRQ0 Rev.3.00 Mar. 26, 2007 Page 95 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.3 Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ5, IRQ4, IRQ1 and IRQ0) and 25 internal interrupts. 5.3.1 External Interrupts There are five external interrupts: NMI, and IRQ5, IRQ4, IRQ1, and IRQ0. Of these, NMI, IRQ0, IRQ1, can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, regardless of the states of the I and UI bits in CCR. The NMIEG bit in SYSCR selects whether an interrupt is requested by the rising or falling edge of the input at the NMI pin. NMI interrupt exception handling has vector number 7. IRQ5, IRQ4, IRQ1, IRQ0 Interrupts: These interrupts are requested by input signals at pins IRQ5, IRQ4, IRQ1, IRQ0. The IRQ5, IRQ4, IRQ1, IRQ0 interrupts have the following features. * ISCR settings can select whether an interrupt is requested by the low level of the input at pins IRQ5, IRQ4, IRQ1, IRQ0, or by the falling edge. * IER settings can enable or disable the IRQ5, IRQ4, IRQ1, IRQ0 interrupts. Interrupt priority levels can be assigned by four bits in IPRA (IPRA7, IPRA6, and IPRA4). * The status of IRQ5, IRQ4, IRQ1, IRQ0 interrupt requests is indicated in ISR. The ISR flags can be cleared to 0 by software. Figure 5.2 shows a block diagram of interrupts IRQ5, IRQ4, IRQ1, IRQ0. IRQnSC IRQnF Edge/level sense circuit IRQn input S R Clear signal Note: n = 5, 4, 1 and 0 Q IRQn interrupt request IRQnE Figure 5.2 Block Diagram of Interrupts IRQ5, IRQ4, IRQ1, and IRQ0 Rev.3.00 Mar. 26, 2007 Page 96 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note: n = 5, 4, 1 and 0 Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ5, IRQ4, IRQ1, IRQ0 have vector numbers 17, 16, 13, 12. These interrupts are detected regardless of whether the corresponding pin is set for input or output. When using a pin for external interrupt input, clear its DDR bit to 0 and do not use the pin for SCI input or output. 5.3.2 Internal Interrupts Twenty-five internal interrupts are requested from the on-chip supporting modules. * Each on-chip supporting module has status flags for indicating interrupt status, and enable bits for enabling or disabling interrupts. * Interrupt priority levels can be assigned in IPRA and IPRB. 5.3.3 Interrupt Vector Table Table 5.3 lists the interrupt sources, their vector addresses, and their default priority order. In the default priority order, smaller vector numbers have higher priority. The priority of interrupts other than NMI can be changed in IPRA and IPRB. The priority order after a reset is the default order shown in table 5.3. Rev.3.00 Mar. 26, 2007 Page 97 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Table 5.3 Interrupt Sources, Vector Addresses, and Priority Vector Number 7 12 13 -- 14 15 Vector Address* Normal Mode Advanced Mode IPR Priority High Interrupt Source NMI IRQ0 IRQ1 Reserved Origin External pins H'000E to H'000F H'001C to H'001F -- H'0018 to H'0019 H'0030 to H'0033 IPRA7 IPRA6 H'001A to H'001B H'0034 to H0037 H'001C to H'001D H'0038 to H'003B -- H'001E to H'001F H'003C to H'003F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 IPRA3 IPRA4 IRQ4 IRQ5 Reserved External pins 16 17 -- 18 19 WOVI (interval timer) Reserved Watchdog timer 20 -- 21 22 23 H'002A to H'002B H'0054 to H'0057 H'002C to H'002D H'0058 to H'005B H'002E to H'002F H'005C to H'005F H'0030 to H'0031 H'0032 to H'0033 H'0034 to H'0035 H'0036 to H'0037 H'0038 to H'0039 H'0060 to H'0063 H'0064 to H'0067 H'0068 to H'006B H'006C to H'006F H'0070 to H'0073 IPRA1 IPRA2 IMIA0 (compare match/ input capture A0) IMIB0 (compare match/ input capture B0) OVI0 (overflow 0) Reserved IMIA1 (compare match/ input capture A1) IMIB1 (compare match/ input capture B1) OVI1 (overflow 1) Reserved IMIA2 (compare match/ input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved ITU channel 0 24 25 26 -- ITU channel 1 27 28 29 30 H'003A to H'003B H'0074 to H'0077 H'003C to H'003D H'0078 to H'007B H'003E to H'003F H'007C to H'007F H'0040 to H'0041 H'0042 to H'0043 H'0044 to H'0045 H'0046 to H'0047 H'0080 to H'0083 H'0084 to H'0087 H'0088 to H'008B H'008C to H'008F IPRA0 -- ITU channel 2 31 32 33 34 -- 35 Rev.3.00 Mar. 26, 2007 Page 98 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Vector Number 36 37 38 -- ITU channel 4 39 40 41 42 -- 43 44 45 46 47 48 49 50 51 ERI0 (receive error 0) RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 (receive error 1) RXI1 (receive data full 1) TXI1 (transmit data empty 1) TEI1 (transmit end 1) ADI (A/D end) A/D SCI channel 1 SCI channel 0 52 53 54 55 56 57 58 59 60 Vector Address* Normal Mode H'0048 to H'0049 Advanced Mode H'0090 to H'0093 IPR IPRB7 Priority Interrupt Source IMIA3 (compare match/ input capture A3) IMIB3 (compare match/ input capture B3) OVI3 (overflow 3) Reserved IMIA4 (compare match/ input capture A4) IMIB4 (compare match/ input capture B4) OVI4 (overflow 4) Reserved Origin ITU channel 3 H'004A to H'004B H'0094 to H'0097 H'004C to H'004D H'0098 to H'009B H'004E to H'004F H'009C to H'009F H'0050 to H'0051 H'0052 to H'0053 H'0054 to H'0055 H'0056 to H'0057 H'0058 to H'0059 H'00A0 to H'00A3 IPRB6 H'00A4 to H'00A7 H'00A8 to H'00AB H'00AC to H'00AF -- H'00B0 to H'00B3 H'005A to H'005B H'00B4 to H'00B7 H'005C to H'005D H'00B8 to H'00BB H'005E to H'005F H'00BC to H'00BF H'0060 to H'0061 H'0062 to H'0063 H'0064 to H'0065 H'0066 to H'0067 H'0068 to H'0069 H'00C0 to H'00C3 H'00C4 to H'00C7 H'00C8 to H'00CB H'00CC to H'00CF H'00D0 to H'00D3 IPRB3 H'006A to H'006B H'00D4 to H'00D7 H'006C to H'006D H'00D8 to H'00DB H'006E to H'006F H'00DC to H'00DF H'0070 to H'0071 H'0072 to H'0073 H'0074 to H'0075 H'0076 to H'0077 H'0078 to H'0079 H'00E0 to H'00E3 IPRB2 H'00E4 to H'00E7 H'00E8 to H'00EB H'00EC to H'00EF H'00F0 to H'00F3 IPRB1 Low Note: * Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 99 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.4 5.4.1 Interrupt Operation Interrupt Handling Process The H8/3039 Group handles interrupts differently depending on the setting of the UE bit. When UE = 1, interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits. Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI bits. NMI interrupts are always accepted except in the reset and hardware standby states. IRQ interrupts and interrupts from the on-chip supporting modules have their own enable bits. Interrupt requests are ignored when the enable bits are cleared to 0. Table 5.4 SYSCR UE 1 I 0 1 0 0 1 UE, I, and UI Bit Settings and Interrupt Handling CCR UI -- -- -- 0 1 Description All interrupts are accepted. Interrupts with priority level 1 have higher priority. No interrupts are accepted except NMI. All interrupts are accepted. Interrupts with priority level 1 have higher priority. NMI and interrupts with priority level 1 are accepted. No interrupts are accepted except NMI. UE = 1 Interrupts IRQ0, IRQ1, IRQ4, and IRQ5 and interrupts from the on-chip supporting modules can all be masked by the I bit in the CPU's CCR. Interrupts are masked when the I bit is set to 1, and unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority. Figure 5.4 is a flowchart showing how interrupts are accepted when UE = 1. Rev.3.00 Mar. 26, 2007 Page 100 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Program execution state No Interrupt requested? Yes Yes NMI? No No Priority level 1? Yes No No Pending IRQ0? Yes IRQ0? No Yes IRQ1? Yes IRQ1? Yes No ADI? Yes ADI? Yes No I = 0? Yes Save PC and CCR I 1 Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when UE = 1 Rev.3.00 Mar. 26, 2007 Page 101 of 682 REJ09B0353-0300 Section 5 Interrupt Controller * If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted. If the I bit is set to 1, only NMI is accepted; other interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * Next the I bit is set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. UE = 0 The I and UI bits in the CPU's CCR and the IPR bits enable three-level masking of IRQ0, IRQ1, IRQ4, and IRQ5 interrupts and interrupts from the on-chip supporting modules. * Interrupt requests with priority level 0 are masked when the I bit is set to 1, and are unmasked when the I bit is cleared to 0. * Interrupt requests with priority level 1 are masked when the I and UI bits are both set to 1, and are unmasked when either the I bit or the UI bit is cleared to 0. For example, if the interrupt enable bits of all interrupt requests are set to 1, IPRA is set to H'10, and IPRB is set to H'00 (giving IRQ4 and IRQ5 interrupt requests priority over other interrupts), interrupts are masked as follows: a. If I = 0, all interrupts are unmasked (priority order: NMI > IRQ4 > IRQ5 > IRQ0 ...). b. If I = 1 and UI = 0, only NMI, IRQ4, and IRQ5 are unmasked. c. If I = 1 and UI = 1, all interrupts are masked except NMI. Figure 5.5 shows the transitions among the above states. Rev.3.00 Mar. 26, 2007 Page 102 of 682 REJ09B0353-0300 Section 5 Interrupt Controller I0 a. All interrupts are unmasked I 1, UI 0 b. Only NMI, IRQ 4 , and IRQ 5 are unmasked I0 Exception handling, or I 1, UI 1 UI 0 Exception handling, or UI 1 c. All interrupts are masked except NMI Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5.6 is a flowchart showing how interrupts are accepted when UE = 0. * If an interrupt condition occurs and the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. * When the interrupt controller receives one or more interrupt requests, it selects the highestpriority request, following the IPR interrupt priority settings, and holds other requests pending. If two or more interrupts with the same IPR setting are requested simultaneously, the interrupt controller follows the priority order shown in table 5.3. * The interrupt controller checks the I bit. If the I bit is cleared to 0, the selected interrupt request is accepted regardless of its IPR setting, and regardless of the UI bit. If the I bit is set to 1 and the UI bit is cleared to 0, only NMI and interrupts with priority level 1 are accepted; interrupt requests with priority level 0 are held pending. If the I bit and UI bit are both set to 1, only NMI is accepted; all other interrupt requests are held pending. * When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. * In interrupt exception handling, PC and CCR are saved to the stack area. The PC value that is saved indicates the address of the first instruction that will be executed after the return from the interrupt service routine. * The I and UI bits are set to 1 in CCR, masking all interrupts except NMI. * The vector address of the accepted interrupt is generated, and the interrupt service routine starts executing from the address indicated by the contents of the vector address. Rev.3.00 Mar. 26, 2007 Page 103 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Program execution state No Interrupt requested? Yes Yes NMI? No No Priority level 1? Yes No No Pending IRQ0? Yes IRQ0? No Yes IRQ1? Yes IRQ1? Yes No ADI? Yes ADI? Yes No I = 0? Yes No UI = 0? Yes I = 0? Yes No Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt service routine Figure 5.6 Process Up to Interrupt Acceptance when UE = 0 Rev.3.00 Mar. 26, 2007 Page 104 of 682 REJ09B0353-0300 5.4.2 Interrupt accepted Interrupt level decision and wait for end of instruction Instruction Internal prefetch processing Stack Vector fetch Prefetch of interrupt Internal service routine processing instruction Interrupt Sequence Interrupt request signal (1) (3) (5) (7) (9) (11) (13) Address bus Internal read signal High (2) (4) (6) (8) (10) (12) (14) Internal write signal Internal data bus (1) Instruction prefetch address (not executed; return address, same as PC contents) (2), (4) Instruction code (not executed) (3) Instruction prefetch address (not executed) (5) SP - 2 (7) SP - 4 (6), (8) PC and CCR saved to stack (9), (11) Vector address (10), (12) Starting address of interrupt service routine (contents of vector address) (13) Starting address of interrupt service routine; (13) = (10), (12) (14) First instruction of interrupt service routine Figure 5.7 shows the interrupt sequence in mode 5 when the program code and stack are in an onchip memory area. Figure 5.7 Interrupt Sequence (Mode 5, Stack in On-Chip Memory) Rev.3.00 Mar. 26, 2007 Page 105 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Note: Mode 5, with program code and stack in on-chip memory area. Section 5 Interrupt Controller 5.4.3 Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time External Memory On-Chip Memory 2* 1 8-Bit Bus 2 States 2* 1 No. 1 2 Item Interrupt priority decision Maximum number of states until end of current instruction 3 States 2* 1 4 1 to 23 1 to 27 1 to 31* 4 4 4 3 4 5 6 Total Saving PC and CCR to stack Vector fetch Instruction prefetch* Internal processing* 2 3 4 4 4 4 19 to 41 8 8 8 4 31 to 57 12* 12* 12* 4 43 to 73 Notes: 1. 1 state for internal interrupts. 2. Prefetch after the interrupt is accepted and prefetch of the first instruction in the interrupt service routine. 3. Internal processing after the interrupt is accepted and internal processing after prefetch. 4. The number of states increases if wait states are inserted in external memory access. Rev.3.00 Mar. 26, 2007 Page 106 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.5 5.5.1 Usage Notes Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit to 0 to disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed. If an interrupt occurs while a BCLR, MOV, or other instruction is being executed to clear its interrupt enable bit to 0, at the instant when execution of the instruction ends the interrupt is still enabled, so its interrupt exception handling is carried out. If a higher-priority interrupt is also requested, however, interrupt exception handling for the higher-priority interrupt is carried out, and the lower-priority interrupt is ignored. This also applies to the clearing of an interrupt flag. Figure 5.8 shows an example in which an IMIEA bit is cleared to 0 in the ITU's TIER. TIER write cycle by CPU Internal address bus Internal write signal IMIEA IMIA exception handling TIER address IMIA IMFA interrupt signal Figure 5.8 Contention between Interrupt and Interrupt-Disabling Instruction This type of contention will not occur if the interrupt is masked when the interrupt enable bit or flag is cleared to 0. Rev.3.00 Mar. 26, 2007 Page 107 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 5.5.2 Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting instructions, however, when the instruction is completed the CPU always continues by executing the next instruction. 5.5.3 Interrupts during EEPMOV Instruction Execution The EEPMOV.B and EEPMOV.W instructions differ in their reaction to interrupt requests. When the EEPMOV.B instruction is executing a transfer, no interrupts are accepted until the transfer is completed, not even NMI. When the EEPMOV.W instruction is executing a transfer, interrupt requests other than NMI are not accepted until the transfer is completed. If NMI is requested, NMI exception handling starts at a transfer cycle boundary. The PC value saved on the stack is the address of the next instruction. Programs should be coded as follows to allow for NMI interrupts during EEPMOV.W execution: L1: EEPMO V.W MOV.W R4, R4 BNE L1 5.5.4 Usage Notes The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read while set to 1. However, it is possible for the IRQnF flag to be cleared by mistake simply by writing 0 to it, irrespective of whether it has been read while set to 1, with the result that interrupt exception handling is not executed. This will occur when the following conditions are met. 1. Setting Conditions (1) Multiple external interrupts (IRQa, IRQb) are being used. (2) Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and clearing by hardware for the IRQbF flag. (3) A bit-manipulation instruction is used on the IRQ status register for clearing the IRQaF flag, or else ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values read in the other bits are written as a byte unit. Rev.3.00 Mar. 26, 2007 Page 108 of 682 REJ09B0353-0300 Section 5 Interrupt Controller 2. Generation Conditions (1) A read of the ISR register is executed to clear the IRQaF flag while it is set to 1, then the IRQbF flag is cleared by the execution of interrupt exception handling. (2) When the IRQaF flag is cleared, there is contention with IRQb generation (IRQaF flag setting). (IRQbF was 0 when ISR was read to clear the IRQaF flag, but IRQbF is set to 1 before ISR is written to.) If the above setting conditions (1) to (3) and generation conditions (1) and (2) are all fulfilled, when the ISR write in generation condition (2) is performed the IRQbF flag will be cleared inadvertently, and interrupt exception handling will not be executed. However, this inadvertent clearing of the IRQbF flag will not occur if 0 is written to this flag even once between generation conditions (1) and (2). IRQaF 1 read 0 written 1 read 0 written IRQbF 1 read 1 IRQb written executed 1 read 0 written (Inadvertent clearing) Generation condition (1) Generation condition (2) Figure 5.9 IRQnF Flag when Interrupt Exception Handling is not Executed Rev.3.00 Mar. 26, 2007 Page 109 of 682 REJ09B0353-0300 Section 5 Interrupt Controller Either of the methods shown below should be used to prevent this problem. Method 1: When clearing the IRQaF flag, read ISR as a byte unit instead of using a bitmanipulation instruction, and write a byte value that clears the IRQaF flag to 0 and sets the other bits to 1. Example: When a = 0 MOV.B @ISR, R0L MOV.B #HFE, R0L MOV.B R0L, @ISR Method 2: Perform dummy processing within the IRQb interrupt exception handling routine to clear the IRQbF flag. Example: When b = 1 IRQB MOV.B #HFD, R0L MOV.B R0L, @ISR Rev.3.00 Mar. 26, 2007 Page 110 of 682 REJ09B0353-0300 Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The H8/3039 Group has an on-chip bus controller that divides the external address space into eight areas and can assign different bus specifications to each. This enables different types of memory to be connected easily. 6.1.1 Features Features of the bus controller are listed below. * Independent settings for address areas 0 to 7 128-kbyte areas in 1-Mbyte mode. 2-Mbyte areas in 16-Mbyte mode. Areas can be designated for two-state or three-state access. * Four wait modes Programmable wait mode, pin auto-wait mode, and pin wait modes 0 and 1 can be selected. Zero to three wait states can be inserted automatically. Rev.3.00 Mar. 26, 2007 Page 111 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. ASTCR Internal address bus WCER Area decoder Internal signals Access state control signal Wait request signal WAIT Wait-state controller WCR Legend: ASTCR: Access state control register WCER: Wait state controller enable register WCR: Wait control register Figure 6.1 Block Diagram of Bus Controller Rev.3.00 Mar. 26, 2007 Page 112 of 682 REJ09B0353-0300 Internal data bus Bus control circuit Section 6 Bus Controller 6.1.3 Input/Output Pins Table 6.1 summarizes the bus controller's input/output pins. Table 6.1 Name Address strobe Read Write Bus Controller Pins Abbreviation AS RD WR I/O Output Output Output Function Strobe signal indicating valid address output on the address bus Strobe signal indicating reading from the external address space Strobe signal indicating writing to the external address space, with valid data on the data bus(D7 to D0) Wait request signal for access to external threestate-access areas Wait WAIT Input 6.1.4 Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Address* H'FFED H'FFEE H'FFEF H'FFF3 Note: * Bus Controller Registers Name Access state control register Wait control register Wait state controller enable register Address control register Lower 16 bits of the address. Abbreviation ASTCR WCR WCER ADRCR R/W R/W R/W R/W R/W Initial Value H'FF H'F3 H'FF H'FE Rev.3.00 Mar. 26, 2007 Page 113 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.2 6.2.1 Register Descriptions Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states. Bit Initial value Read/Write 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Bits selecting number of states for access to each area ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is accessed in two or three states. Bits 7 to 0 AST7 to AST0 0 1 Description Areas 7 to 0 are accessed in two states Areas 7 to 0 are accessed in three states (Initial value) ASTCR specifies the number of states in which external areas are accessed. On-chip memory and registers are accessed in a fixed number of states that does not depend on ASTCR settings. Therefore, in the single-chip modes (modes 6 and 7), the set value is meaningless. Rev.3.00 Mar. 26, 2007 Page 114 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.2.2 Wait Control Register (WCR) WCR is an 8-bit readable/writable register that selects the wait mode for the wait-state controller (WSC) and specifies the number of wait states. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 WMS1 0 R/W 2 WMS0 0 R/W 1 WC1 1 R/W 0 WC0 1 R/W Reserved bits Wait count 1/0 These bits select the number of wait states inserted Wait mode select 1/0 These bits select the wait mode WCR is initialized to H'F3 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bits 3 and 2--Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode. Bit3 WMS1 0 Bit2 WMS0 0 1 1 0 1 Description Programmable wait mode No wait states inserted by wait-state controller Pin wait mode 1 Pin auto-wait mode (Initial value) Rev.3.00 Mar. 26, 2007 Page 115 of 682 REJ09B0353-0300 Section 6 Bus Controller Bits 1 and 0--Wait Count 1 and 0 (WC1/0): These bits select the number of wait states inserted in access to external three-state-access areas. Bit1 WC1 0 Bit0 WC0 0 1 1 0 1 Description No wait states inserted by wait-state controller 1 state inserted 2 states inserted 3 states inserted (Initial value) 6.2.3 Wait State Controller Enable Register (WCER) WCER is an 8-bit readable/writable register that enables or disables wait-state control of external three-state-access areas by the wait-state controller. Bit Initial value Read/Write 7 WCE7 1 R/W 6 WCE6 1 R/W 5 WCE5 1 R/W 4 WCE4 1 R/W 3 WCE3 1 R/W 2 WCE2 1 R/W 1 WCE1 1 R/W 0 WCE0 1 R/W Wait state controller enable 7 to 0 These bits enable or disable wait-state control WCER is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Wait-State Controller Enable 7 to 0 (WCE7 to WCE0): These bits enable or disable wait-state control of external three-state-access areas. Bits 7 to 0 WCE7 to WCE0 0 1 Description Wait-state control disabled (pin wait mode 0) Wait-state control enabled (Initial value) WCER enables or disables wait-state control of external three-state-access areas. Therefore, in the single-chip modes (modes 6 and 7), the set value is meaningless. Rev.3.00 Mar. 26, 2007 Page 116 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.2.4 Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that enables address output on bus lines A23 to A21. Bit Initial value Initial value Read/Write 7 A23E Modes 1 and 5 to 7 Read/Write Mode 3 1 -- 1 R/W 6 A22E 1 -- 1 R/W 5 A21E 1 -- 1 R/W 4 -- 1 -- 1 -- 3 -- 1 -- 1 -- 2 -- 1 -- 1 -- Reserved bits 1 -- 1 -- 1 -- 0 -- 0 R/W 0 R/W Address 23 to 21 enable These bits enable PA6 to PA4 to be used for A23 to A21 address output ADRCR is initialized to H'FE by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Address 23 Enable (A23E): Enables PA4 to be used as the A23 address output pin. Writing 0 in this bit enables A23 address output from PA4. In modes other than 3 this bit cannot be modified and PA4 has its ordinary input/output functions Bit 7 A23E 0 1 Description PA4 is the A23 address output pin PA4 is the PA4/TP4/TIOCA1 input/output pin (Initial value) Bit 6--Address 22 Enable (A22E): Enables PA5 to be used as the A22 address output pin. Writing 0 in this bit enables A22 address output from PA5. In modes other than 3 this bit cannot be modified and PA5 has its ordinary input/output functions. Bit 6 A22E 0 1 Description PA5 is the A22 address output pin PA5 is the PA5/TP5/TIOCB1 input/output pin (Initial value) Rev.3.00 Mar. 26, 2007 Page 117 of 682 REJ09B0353-0300 Section 6 Bus Controller Bit 5--Address 21 Enable (A21E): Enables PA6 to be used as the A21 address output pin. Writing 0 in this bit enables A21 address output from PA6. In modes other than 3 this bit cannot be modified and PA6 has its ordinary input/output functions. Bit 5 A21E 0 1 Description PA6 is the A21 address output pin PA6 is the PA6/TP6/TIOCA2 input/output pin (Initial value) Bits 4 to 0--Reserved Rev.3.00 Mar. 26, 2007 Page 118 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.3 6.3.1 Operation Area Division The external address space is divided into areas 0 to 7. Each area has a size of 128 kbytes in the 1-Mbyte mode and 2 Mbytes in the 16-Mbyte mode. Figure 6.2 shows a general view of the memory map. H'00000 Area 0 (128 kbytes) H'1FFFF H'20000 Area 1 (128 kbytes) H'3FFFF H'40000 Area 2 (128 kbytes) H'5FFFF H'60000 Area 3 (128 kbytes) H'7FFFF H'80000 Area 4 (128 kbytes) H'9FFFF H'A0000 Area 5 (128 kbytes) H'BFFFF H'C0000 Area 6 (128 kbytes) H'DFFFF H'E0000 Area 7 (128 kbytes) On-chip RAM *1 *2 H'DFFFFF H'E00000 H'BFFFFF H'C00000 Area 6 (2 Mbytes) Area 7 (2 Mbytes) On-chip RAM*1 *2 H'DFFFF H'E0000 H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFF H'C0000 Area 6 (128 kbytes) Area 7 (128 kbytes) On-chip RAM*1 *2 External address space*3 H'FFFFF On-chip I/O registers*1 c. 1-Mbyte mode with on-chip ROM enabled (mode 5) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFF H'A0000 Area 5 (128 kbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFF H'80000 Area 4 (128 kbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFF H'60000 Area 3 (128 kbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFF H'40000 Area 2 (128 kbytes) H'000000 Area 0 (2 Mbytes) H'1FFFF H'20000 Area 0 (128 kbytes) Area 1 (128 kbytes) H'00000 On-chip ROM*1 External address space*3 H'FFFFF On-chip I/O registers*1 a. 1-Mbyte modes with on-chip ROM disabled (mode 1) External address space*3 *1 H'FFFFFF On-chip I/O registers b. 16-Mbyte modes with on-chip ROM disabled (mode 3) Notes: There is no area division in modes 6 and 7. 1. The number of access states to on-chip ROM, on-chip RAM, and on-chip I/O registers is fixed. 2. This area follows area 7 specifications when the RAME bit in SYSCR is 0. 3. This area follows area 7 specifications. Figure 6.2 Access Area Map (Mode 1, 3, and 5) Rev.3.00 Mar. 26, 2007 Page 119 of 682 REJ09B0353-0300 Section 6 Bus Controller The bus specifications for each area can be selected in ASTCR, WCER, and WCR as shown in table 6.3. Table 6.3 ASTCR ASTn 0 1 Bus Specifications WCER WCEn -- 0 1 WMS1 -- -- 0 WCR WMS0 -- -- 0 1 1 0 1 Bus Width 8 8 8 8 8 8 Access States 2 3 3 3 3 3 Bus Specifications Wait Mode Disabled Pin wait mode 0 Programmable wait mode Disabled Pin wait mode 1 Pin auto-wait mode Note: n = 0 to 7 Rev.3.00 Mar. 26, 2007 Page 120 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.3.2 Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.3 shows the timing of bus control signals for an 8-bit, three-state-access area. Wait states can be inserted. Bus cycle T1 T2 T3 Address bus External address AS RD Read access D7 to D0 Valid WR Write access D7 to D0 Valid Figure 6.3 Bus Control Signal Timing for 8-Bit, Three-State-Access Area Rev.3.00 Mar. 26, 2007 Page 121 of 682 REJ09B0353-0300 Section 6 Bus Controller 8-Bit, Two-State-Access Areas Figure 6.4 shows the timing of bus control signals for an 8-bit, two-state-access area. Wait states cannot be inserted. Bus cycle T1 T2 Address bus External address AS RD Read access D7 to D0 Valid WR Write access D7 to D0 Valid Figure 6.4 Bus Control Signal Timing for 8-Bit, Two-State-Access Area Rev.3.00 Mar. 26, 2007 Page 122 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.3.3 Wait Modes Four wait modes can be selected for each area as shown in table 6.4. Table 6.4 ASTCR ASTn Bit 0 1 Wait Mode Selection WCER WCEn Bit -- 0 1 WMS1 Bit -- -- 0 WCR WMS0 Bit -- -- 0 1 1 0 1 WSC Control Disabled Disabled Enabled Enabled Enabled Enabled Wait Mode No wait states Pin wait mode 0 Programmable wait mode No wait states Pin wait mode 1 Pin auto-wait mode Note: n = 0 to 7 The ASTn and WCEn bits can be set independently for each area. Bits WMS1 and WMS0 apply to all areas. All areas for which WSC control is enabled operate in the same wait mode. Rev.3.00 Mar. 26, 2007 Page 123 of 682 REJ09B0353-0300 Section 6 Bus Controller Pin Wait Mode 0 The wait state controller is disabled. Wait states can only be inserted by WAIT pin control. During access to an external three-state-access area, if the WAIT pin is low at the fall of the system clock () in the T2 state, a wait state (TW) is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Figure 6.5 shows the timing. Inserted by WAIT signal T1 T2 TW TW T3 * * * WAIT pin Address bus AS RD Read access Data bus WR Write access Data bus Note: * Arrows indicate time of sampling of the WAIT pin. Write data Read data External address Figure 6.5 Pin Wait Mode 0 Rev.3.00 Mar. 26, 2007 Page 124 of 682 REJ09B0353-0300 Section 6 Bus Controller Pin Wait Mode 1 In all accesses to external three-state-access areas, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. If the WAIT pin is low at the fall of the system clock () in the last of these wait states, an additional wait state is inserted. If the WAIT pin remains low, wait states continue to be inserted until the WAIT signal goes high. Pin wait mode 1 is useful for inserting four or more wait states, or for inserting different numbers of wait states for different external devices. If the wait count is 0, this mode operates in the same way as pin wait mode 0. Figure 6.6 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional wait state is inserted by WAIT input. Inserted by wait count T1 T2 TW Inserted by WAIT signal TW T3 * * WAIT pin Address bus AS RD Read data Data bus WR Write access Data bus Note: * Arrows indicate time of sampling of the WAIT pin. Write data External address Read access Figure 6.6 Pin Wait Mode 1 Rev.3.00 Mar. 26, 2007 Page 125 of 682 REJ09B0353-0300 Section 6 Bus Controller Pin Auto-Wait Mode If the WAIT pin is low, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. In pin auto-wait mode, if the WAIT pin is low at the fall of the system clock () in the T2 state, the number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait states are inserted even if the WAIT pin remains low. Figure 6.7 shows the timing when the wait count is 1. T1 T2 T3 T1 T2 TW T3 * * WAIT Address bus External address External address AS RD Read access Data bus Read data Read data WR Write access Data bus Write data Write data Note: * Arrows indicate time of sampling of the WAIT pin. Figure 6.7 Pin Auto-Wait Mode Rev.3.00 Mar. 26, 2007 Page 126 of 682 REJ09B0353-0300 Section 6 Bus Controller Programmable Wait Mode The number of wait states (TW) selected by bits WC1 and WC0 are inserted in all accesses to external three-state-access areas. Figure 6.8 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1). T1 T2 TW T3 Address bus External address AS RD Read access Data bus Read data WR Write access Data bus Write data Figure 6.8 Programmable Wait Mode Rev.3.00 Mar. 26, 2007 Page 127 of 682 REJ09B0353-0300 Section 6 Bus Controller Example of Wait State Control Settings A reset initializes ASTCR and WCER to H'FF and WCR to H'F3, selecting programmable wait mode and three wait states for all areas. Software can select other wait modes for individual areas by modifying the ASTCR, WCER, and WCR settings. Figure 6.9 shows an example of wait mode settings. Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 3-state-access area, programmable wait mode 3-state-access area, programmable wait mode 3-state-access area, pin wait mode 0 3-state-access area, pin wait mode 0 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted 2-state-access area, no wait states inserted Bit: ASTCR H'0F: 7 0 6 0 5 0 4 0 3 1 2 1 1 1 0 1 WCER H'33: 0 0 1 1 0 0 1 1 WCR H'F3: -- -- -- -- 0 0 1 1 Note: Wait states cannot be inserted in areas designated for two-state access by ASTCR. Figure 6.9 Wait Mode Settings (Example) Rev.3.00 Mar. 26, 2007 Page 128 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.3.4 Interconnections with Memory (Example) For each area, the bus controller can select two- or three-state access. In three-state-access areas, wait states can be inserted in a variety of modes, simplifying the connection of both high-speed and low-speed devices. Figure 6.10 shows a memory map for this example. A 32-kword x 8-bit EPROM is connected to area 2. This device is accessed in three states via an 8-bit bus. Two 32-kword x 8-bit SRAM devices (SRAM1 and SRAM2) are connected to area 3. These devices are accessed in two states via an 8-bit bus. One 32-kword x 8-bit SRAM (SRAM3) is connected to area 7. This device is accessed via an 8-bit bus, using three-state access with an additional wait state inserted in pin auto-wait mode. Rev.3.00 Mar. 26, 2007 Page 129 of 682 REJ09B0353-0300 Section 6 Bus Controller H'00000 H'1FFFF H'20000 H'3FFFF H'40000 H'47FFF H'48000 H'5FFFF H'60000 On-chip ROM Area 0 Area 1 EPROM Not used SRAM1, 2 Area 2 8-bit, three-state-access area H'6FFFF H'70000 Not used H'7FFFF Area 3 8-bit, two-state-access area Areas 4, 5, 6 H'E0000 SRAM3 H'E7FFF Not used On-chip RAM H'FFFFF On-chip I/O registers Area 7 8-bit, three-state-access area (one auto-wait state) Note: The bus width and the number of access states of the on-chip memories and I/O registers are fixed; they cannot be changed by register setting. Figure 6.10 Memory Map (H8/3039 Mode 5) Rev.3.00 Mar. 26, 2007 Page 130 of 682 REJ09B0353-0300 Section 6 Bus Controller 6.4 6.4.1 Usage Notes Register Write Timing ASTCR and WCER Write Timing Data written to ASTCR or WCER takes effect starting from the next bus cycle. Figure 6.11 shows the timing when an instruction fetched from area 2 changes area 2 from three-state access to twostate access. T1 Address 3-state access to area 2 ASTCR address T2 T3 T1 T2 T3 T1 T2 2-state access to area 2 Figure 6.11 ASTCR Write Timing 6.4.2 Precautions on Setting ASTCR and ABWCR* Use the H8/3039 Group on-chip program to set ASTCR and ABWCR as shown below, so that the on-chip ROM access cycle for H8/3039 Group can be emulated using the evaluation chip for support tools. Modes 5 and 7 ASTCR0 = 0 ABWCR = H'FC Note: * The ABWCR (bus width control register; lower 16-bit address: H'FFEC) is not built onto this LSI. For detailed features of the ABWCR, see the H8/3048 Group, TM H8/3048F-ZTAT Hardware Manual. Rev.3.00 Mar. 26, 2007 Page 131 of 682 REJ09B0353-0300 Section 6 Bus Controller Rev.3.00 Mar. 26, 2007 Page 132 of 682 REJ09B0353-0300 Section 7 I/O Ports Section 7 I/O Ports 7.1 Overview The H8/3039 Group has nine input/output ports (ports 1, 2, 3, 5, 6, 8, 9, A, and B) and one input port (port 7). Table 7.1 summarizes the port functions. The pins in each port are multiplexed as shown in table 7.1. Each port has a data direction register (DDR) for selecting input or output, and a data register (DR) for storing output data. In addition to these registers, ports 2, and 5 have an input pull-up control register (PCR) for switching input pull-up transistors on and off. Ports 1 to 3 and ports 5, 6, and 8 can drive one TTL load and a 90-pF capacitive load. Ports 9, A, and B can drive one TTL load and a 30-pF capacitive load. Ports 1 to 3 and ports 5, 6, 8, 9, A, and B can drive a Darlington pair. Ports 1, 2, 5, and B can drive LEDs (with 10-mA current sink). Pins P81, P80, PA7 to PA0, and PB3 to PB0 have Schmitt-trigger input circuits. For block diagrams of the ports see appendix C, I/O Block Diagrams. Rev.3.00 Mar. 26, 2007 Page 133 of 682 REJ09B0353-0300 Section 7 I/O Ports Table 7.1 Port Port Functions Pins Mode 1 Address output pins (A7 to A0) Mode 3 Mode 5 Address output (A7 to A0) and generic input DDR = 0: generic input DDR = 1: address output Mode 6 Mode 7 Description Port 1 * 8-bit I/O port P17 to P10/ A7 to A0 * Can drive LEDs Generic input/ output Port 2 * 8-bit I/O port P27 to P20/ * Input pull-up A15 to A8 * Can drive LEDs Address output pins (A15 to A8) Address output (A15 to A8) and generic input DDR = 0: generic input DDR = 1: address output Generic input/ output Port 3 * 8-bit I/O port P37 to P30/ D7 to D0 Port 5 * 4-bit I/O port P53 to P50/ * Input pull-up A19 to A16 * Can drive LEDs Data input/output (D7 to D0) Address output (A19 to A16) Address output (A19 to A16) and 4-bit generic input DDR = 0: generic input DDR = 1: address output Generic input/ output Generic input/ output Port 6 * 4-bit I/O port P65/WR, P64/RD, P63/AS P60/WAIT Port 7 * 8-bit Input port P77 to P70/ AN7 to AN0 Bus control signal output (WR, RD, AS) Generic input/ output Bus control signal input/output (WAIT) and 1-bit generic input/output Analog input (AN7 to AN0) to A/D converter, and generic input IRQ1 input and 1-bit generic input/output IRQ0 input and 1-bit generic input/output IRQ1 and IRQ0 input and generic input/ output Port 8 * 2-bit I/O port P81/ IRQ1 * P81 and P80 have Schmitt P80/IRQ0 inputs Rev.3.00 Mar. 26, 2007 Page 134 of 682 REJ09B0353-0300 Section 7 I/O Ports Port Description Pins Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Port 9 * 6-bit I/O port P95/SCK1/IRQ5, Input and output (SCK1, SCK0, RxD1, RxD0, TxD1, TxD0) for serial P94/SCK0/IRQ4, communication interfaces 1 and 0 (SCI0, 1), IRQ5 and IRQ4 input, and 6-bit generic input/output P93/RxD1, P92/RxD0, P91/TxD1, P90/TxD0 Output (TP7) Address output (A20) from programmable timing pattern controller (TPC), input or output (TIOCB2) for 16-bit integrated timer unit (ITU), and generic input/output TPC output (TP6 to TP4), ITU input and output (TIOCA2, TIOCB1, TIOCA1), and generic input/ output TPC output (TP6 to TP4), ITU input and output (TIOCA2, TIOCB1, TIOCA1), address output (A23 to A21), and generic input/output TPC output (TP7), ITU input or output (TIOCB2), and generic input/output Port A * 8-bit I/O port PA7/TP7/ TIOCB2/A20 * Schmitt inputs PA6/TP6/ TIOCA2/A21, PA5/TP5/ TIOCB1/A22, PA4/TP4/ TIOCA1/A23 TPC output (TP6 to TP4), ITU input and output (TIOCA2, TIOCB1, TIOCA1), and generic input/output PA3/TP3/ TIOCB0/ TCLKD, PA2/TP2/ TIOCA0/ TCLKC, PA1/TP1/ TCLKB, PA0/TP0/ TCLKA TPC output (TP3 to TP0), ITU input and output (TCLKD, TCLKC, TCLKB, TCLKA, TIOCB0, TIOCA0), and generic input/output Rev.3.00 Mar. 26, 2007 Page 135 of 682 REJ09B0353-0300 Section 7 I/O Ports Port Description Pins PB7/TP15/ ADTRG Mode 1 Mode 3 Mode 5 Mode 6 Mode 7 Port B * 7-bit I/Oport * Can drive LEDs TPC output (TP15), trigger input (ADTRG) to A/D converter, and generic input/output. TPC output (TP13 to TP8), ITU input and output (TOCXB4, TOCXA4, TIOCB4, TIOCA4, TIOCB3, TIOCA3), and generic input/output PB5/TP13/ TOCXB4, * PB3 to PB0 have Schmitt PB4/TP12/ TOCXA4 inputs PB3/TP11/ TIOCB4, PB2/TP10/ TIOCA4, PB1/TP9/ TIOCB3, PB0/TP8/ TIOCA3 Rev.3.00 Mar. 26, 2007 Page 136 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.2 7.2.1 Port 1 Overview Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7.1. The pin functions differ between the expanded modes with on-chip ROM disabled, expanded modes with on-chip ROM enabled, and single-chip mode. In modes 1, 3 (expanded modes with on-chip ROM disabled), they are address bus output pins (A7 to A0). In mode 5 (expanded modes with on-chip ROM enabled), settings in the port 1 data direction register (P1DDR) can designate pins for address bus output (A7 to A0) or generic input. In modes 6 and 7 (single-chip mode), port 1 is a generic input/output port. Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. Port 1 pins P17 /A 7 P16 /A 6 P15 /A 5 Port 1 P14 /A 4 P13 /A 3 P12 /A 2 P11 /A 1 P10 /A 0 Modes 1 and 3 Mode 5 A 7 (output) A 6 (output) A 5 (output) A 4 (output) A 3 (output) A 2 (output) A 1 (output) A 0 (output) P17 (input)/A 7 (output) P16 (input)/A 6 (output) P15 (input)/A 5 (output) P14 (input)/A 4 (output) P13 (input)/A 3 (output) P12 (input)/A 2 (output) P11 (input)/A 1 (output) P10 (input)/A 0 (output) Modes 6 and 7 P17 (input/output) P16 (input/output) P15 (input/output) P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7.1 Port 1 Pin Configuration Rev.3.00 Mar. 26, 2007 Page 137 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.2.2 Register Descriptions Table 7.2 summarizes the registers of port 1. Table 7.2 Port 1 Registers Initial Value Address* H'FFC0 H'FFC2 Note: * Name Port 1 data direction register Port 1 data register Abbreviation P1DDR P1DR R/W W R/W Modes 1, 3 H'FF H'00 Modes 5 to 7 H'00 H'00 Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) P1DDR is an 8-bit write-only register that can select input or output for each pin in port 1. Bit Modes Initial value 1, 3 Read/Write Modes Initial value 5 to 7 Read/Write 7 1 -- 0 W 6 1 -- 0 W 5 1 -- 0 W 4 1 -- 0 W 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W 0 1 -- 0 W P1 7 DDR P1 6 DDR P1 5 DDR P1 4 DDR P1 3 DDR P1 2 DDR P1 1 DDR P1 0 DDR Port 1 data direction 7 to 0 These bits select input or output for port 1 pins P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P1DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Rev.3.00 Mar. 26, 2007 Page 138 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 1 Data Register (P1DR) P1DR is an 8-bit readable/writable register that stores data for pins P17 to P10. Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W Port 1 data 7 to 0 These bits store data for port 1 pins When a bit in P1DDR is set to 1, if port 1 is read the value of the corresponding P1DR bit is returned directly, regardless of the actual state of the pin. When a bit in P1DDR is cleared to 0, if port 1 is read the corresponding pin level is read. P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev.3.00 Mar. 26, 2007 Page 139 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.2.3 Pin Functions in Each Mode The pin functions of port 1 differ between mode 1, 3 (expanded mode with on-chip ROM disabled), mode 5 (expanded mode with on-chip ROM enabled), mode 6, and 7 (single-chip mode). The pin functions in each mode are described as follows. Modes 1 and 3 Address output can be selected for each pin in port 1. Figure 7.2 shows the pin functions in modes 1 and 3. A 7 (output) A 6 (output) A 5 (output) Port 1 A 4 (output) A 3 (output) A 2 (output) A 1 (output) A 0 (output) Figure 7.2 Pin Functions in Modes 1 and 3 (Port 1) Mode 5 Address output or generic input can be selected for each pin in port 1. A pin becomes an address output pin if the corresponding P1DDR bit is set to 1, and a generic input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To use a pin for address output, its P1DDR bit must be set to 1. Figure 7.3 shows the pin functions in mode 5. Rev.3.00 Mar. 26, 2007 Page 140 of 682 REJ09B0353-0300 Section 7 I/O Ports When P1DDR = 1 A 7 (output) A 6 (output) A 5 (output) Port 1 A 4 (output) A 3 (output) A 2 (output) A 1 (output) A 0 (output) When P1DDR = 0 P17 (input) P16 (input) P15 (input) P14 (input) P13 (input) P12 (input) P11 (input) P10 (input) Figure 7.3 Pin Functions in Mode 5 (Port 1) Modes 6 and 7 (Single-Chip Mode) Input or output can be selected separately for each pin in port 1. A pin becomes an output pin if the corresponding P1DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.4 shows the pin functions in modes 6 and 7. P17 (input/output) P16 (input/output) P15 (input/output) Port 1 P14 (input/output) P13 (input/output) P12 (input/output) P11 (input/output) P10 (input/output) Figure 7.4 Pin Functions in Modes 6 and 7 (Port 1) Rev.3.00 Mar. 26, 2007 Page 141 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.3 7.3.1 Port 2 Overview Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7.5. Pin functions differ according to operation mode. In modes 1 and 3 (expanded mode with on-chip ROM disabled), port 2 consists of address bus output pins (A15 to A8). In mode 5 (expanded mode with on-chip ROM enabled), settings in the port 2 data direction register (P2DDR) can designate pins for address bus output (A15 to A8) or generic input. In modes 6 and 7 (single-chip mode), port 2 is a generic input/output port. Port 2 has software-programmable built-in pull-up transistors. Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. Port 2 pins P27 /A 15 P26 /A 14 P25 /A 13 Port 2 P24 /A 12 P23 /A 11 P22 /A 10 P21 /A 9 P20 /A 8 Modes 1 and 3 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Modes 5 P27 (input)/A15 (output) P26 (input)/A14 (output) P25 (input)/A13 (output) P24 (input)/A12 (output) P23 (input)/A11 (output) P22 (input)/A10 (output) P21 (input)/A9 (output) P20 (input)/A8 (output) Mode 6 and 7 P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7.5 Port 2 Pin Configuration Rev.3.00 Mar. 26, 2007 Page 142 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.3.2 Register Descriptions Table 7.3 summarizes the registers of port 2. Table 7.3 Port 2 Registers Initial Value Address* H'FFC1 H'FFC3 H'FFD8 Note: * Name Port 2 data direction register Port 2 data register Port 2 input pull-up control register Abbreviation P2DDR P2DR P2PCR R/W W R/W R/W Modes 1 and 3 H'FF H'00 H'00 Modes 5 to 7 H'00 H'00 H'00 Lower 16 bits of the address. Port 2 Data Direction Register (P2DDR) P2DDR is an 8-bit write-only register that can select input or output for each pin in port 2. Bit Modes Initial value 1 and 3 Read/Write Modes Initial value 5 to 7 Read/Write 7 1 -- 0 W 6 1 -- 0 W 5 1 -- 0 W 4 1 -- 0 W 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W 0 1 -- 0 W P2 7 DDR P2 6 DDR P2 5 DDR P2 4 DDR P2 3 DDR P2 2 DDR P2 1 DDR P2 0 DDR Port 2 data direction 7 to 0 These bits select input or output for port 2 pins P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P2DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Rev.3.00 Mar. 26, 2007 Page 143 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 2 Data Register (P2DR) P2DR is an 8-bit readable/writable register that stores data for pins P27 to P20. Bit Initial value Read/Write 7 P2 7 0 R/W 6 P2 6 0 R/W 5 P2 5 0 R/W 4 P2 4 0 R/W 3 P2 3 0 R/W 2 P2 2 0 R/W 1 P2 1 0 R/W 0 P2 0 0 R/W Port 2 data 7 to 0 These bits store data for port 2 pins When a bit in P2DDR is set to 1, if port 2 is read the value of the corresponding P2DR bit is returned directly, regardless of the actual state of the pin. When a bit in P2DDR is cleared to 0, if port 2 is read the corresponding pin level is read. P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 2 Input Pull-Up Control Register (P2PCR) P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 2. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR Port 2 input pull-up control 7 to 0 These bits control input pull-up transistors built into port 2 When a P2DDR bit is cleared to 0 (selecting generic input) in modes 7 to 5, if the corresponding bit from P27PCR to P20PCR is set to 1, the input pull-up transistor is turned on. P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev.3.00 Mar. 26, 2007 Page 144 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.3.3 Pin Functions in Each Mode The pin functions of port 2 differ between mode 1, 3 (expanded mode with on-chip ROM disabled), mode 5 (expanded mode with on-chip ROM enabled), mode 6, and 7 (single-chip mode). The pin functions in each mode are described followings. Modes 1 and 3 Address output can be selected for each pin in port 2. Figure 7.6 shows the pin functions in modes 1 and 3. A 15 (output) A 14 (output) A 13 (output) Port 2 A 12 (output) A 11 (output) A 10 (output) A 9 (output) A 8 (output) Figure 7.6 Pin Functions in Modes 1 and 3 (Port 2) Mode 5 Address output or generic input can be selected for each pin in port 2. A pin becomes an address output pin if the corresponding P2DDR bit is set to 1, and a generic input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To use a pin for address output, its P2DDR bit must be set to 1. Figure 7.7 shows the pin functions in modes 5. Rev.3.00 Mar. 26, 2007 Page 145 of 682 REJ09B0353-0300 Section 7 I/O Ports When P2DDR = 1 A 15 (output) A 14 (output) A 13 (output) Port 2 A 12 (output) A 11 (output) A 10 (output) A 9 (output) A 8 (output) When P2DDR = 0 P27 (input) P26 (input) P25 (input) P24 (input) P23 (input) P22 (input) P21 (input) P20 (input) Figure 7.7 Pin Functions in Modes 1 and 3 (Port 2) Modes 6 and 7 Input or output can be selected separately for each pin in port 2. A pin becomes an output pin if the corresponding P2DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.8 shows the pin functions in modes 6 and 7. P27 (input/output) P26 (input/output) P25 (input/output) P24 (input/output) Port 2 P23 (input/output) P22 (input/output) P21 (input/output) P20 (input/output) Figure 7.8 Pin Functions in Modes 6 and 7 (Port 2) Rev.3.00 Mar. 26, 2007 Page 146 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.3.4 Input Pull-Up Transistors Port 2 has built-in MOS input pull-up transistors that can be controlled by software. These input pull-up transistors can be turned on and off individually. When a P2PCR bit is set to 1 and the corresponding P2DDR bit is cleared to 0, the input pull-up transistor is turned on. The input pull-up transistors are turned off by a reset and in hardware standby mode. In software standby mode they retain their previous state. Table 7.4 summarizes the states of the input pull-up transistors in each mode. Table 7.4 Mode 1 3 5 6 7 Input Pull-Up Transistor States (Port 2) Reset Off Off Hardware Standby Mode Off Off Software Standby Mode Off On/Off Other Modes Off On/Off Legend: Off: The input pull-up transistor is always off. On/Off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0. Otherwise, it is off. Rev.3.00 Mar. 26, 2007 Page 147 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.4 7.4.1 Port 3 Overview Port 3 is an 8-bit input/output port with the pin configuration shown in figure 7.9. Port 3 is a data bus in modes 1, 3 and 5 (expanded modes) and a generic input/output port in mode 6 and 7 (single-chip mode). Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. Port 3 pins P37 /D7 P36 /D6 P35 /D5 Port 3 P34 /D4 P33 /D3 P32 /D2 P31 /D1 P30 /D0 Modes 1, 3 and 5 D7 (input/output) D6 (input/output) D5 (input/output) D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Modes 6 and 7 P37 (input/output) P36 (input/output) P35 (input/output) P34 (input/output) P33 (input/output) P32 (input/output) P31 (input/output) P30 (input/output) Figure 7.9 Port 3 Pin Configuration 7.4.2 Register Descriptions Table 7.5 summarizes the registers of port 3. Table 7.5 Address* H'FFC4 H'FFC6 Note: * Port 3 Registers Name Port 3 data direction register Port 3 data register Lower 16 bits of the address. Abbreviation P3DDR P3DR R/W W R/W Initial Value H'00 H'00 Rev.3.00 Mar. 26, 2007 Page 148 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 3 Data Direction Register (P3DDR) P3DDR is an 8-bit write-only register that can select input or output for each pin in port 3. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR Port 3 data direction 7 to 0 These bits select input or output for port 3 pins Modes 1, 3, and 5: Port 3 functions as a data bus. P3DDR is ignored. Modes 6 and 7: Port 3 functions as an input/output port. A pin in port 3 becomes an output pin if the corresponding P3DDR bit is set to 1, and an input pin if this bit is cleared to 0. P3DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P3DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P3DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 3 Data Register (P3DR) P3DR is an 8-bit readable/writable register that stores data for pins P37 to P30. Bit Initial value Read/Write 7 P3 7 0 R/W 6 P3 6 0 R/W 5 P3 5 0 R/W 4 P3 4 0 R/W 3 P3 3 0 R/W 2 P3 2 0 R/W 1 P3 1 0 R/W 0 P3 0 0 R/W Port 3 data 7 to 0 These bits store data for port 3 pins When a bit in P3DDR is set to 1, if port 3 is read the value of the corresponding P3DR bit is returned directly, regardless of the actual state of the pin. When a bit in P3DDR is cleared to 0, if port 3 is read the corresponding pin level is read. P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev.3.00 Mar. 26, 2007 Page 149 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.4.3 Pin Functions in Each Mode The pin functions of port 3 differ between modes 1, 3 and 5 and modes 6 and 7. The pin functions in each mode are described below. Modes 1, 3 and 5 All pins of port 3 automatically become data input/output pins. Figure 7.10 shows the pin functions in modes 1, 3 and 5. D7 (input/output) D6 (input/output) D5 (input/output) Port 3 D4 (input/output) D3 (input/output) D2 (input/output) D1 (input/output) D0 (input/output) Figure 7.10 Pin Functions in Modes 1, 3 and 5 (Port 3) Rev.3.00 Mar. 26, 2007 Page 150 of 682 REJ09B0353-0300 Section 7 I/O Ports Modes 6 and 7 Input or output can be selected separately for each pin in port 3. A pin becomes an output pin if the corresponding P3DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.11 shows the pin functions in modes 6 and 7. P3 7 (input/output) P3 6 (input/output) P3 5 (input/output) Port 3 P3 4 (input/output) P3 3 (input/output) P3 2 (input/output) P3 1 (input/output) P3 0 (input/output) Figure 7.11 Pin Functions in Modes 6 and 7 (Port 3) Rev.3.00 Mar. 26, 2007 Page 151 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.5 7.5.1 Port 5 Overview Port 5 is a 4-bit input/output port with the pin configuration shown in figure 7.12. The pin functions differ depending on the operating mode. In modes 1, 3 (expanded modes with on-chip ROM disabled), port 5 consists of address output pins (A19 to A16). In modes 5 (expanded modes with on-chip ROM enabled), settings in the port 5 data direction register (P5DDR) designate pins for address bus output (A19 to A16) or generic input. In mode 6 and 7 (single-chip mode), port 5 is a generic input/output port. Port 5 has software-programmable built-in pull-up transistors. Port 5 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or a Darlington transistor pair. Port 5 pins P53 /A 19 Port 5 P52 /A 18 P51 /A 17 P50 /A 16 Modes 1, 3 A19 (output) A18 (output) A17 (output) A16 (output) Mode 5 P5 3 (input)/A19 (output) P5 2 (input)/A18 (output) P5 1 (input)/A17 (output) P5 0 (input)/A16 (output) Modes 6 and 7 P5 3 (input/output) P5 2 (input/output) P5 1 (input/output) P5 0 (input/output) Figure 7.12 Port 5 Pin Configuration Rev.3.00 Mar. 26, 2007 Page 152 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.5.2 Register Descriptions Table 7.6 summarizes the registers of port 5. Table 7.6 Port 5 Registers Initial Value Address* H'FFC8 H'FFCA H'FFDB Note: * Name Port 5 data direction register Port 5 data register Port 5 input pull-up control register Abbreviation P5DDR P5DR P5PCR R/W W R/W R/W Modes 1 and 3 H'FF H'F0 H'F0 Modes 5 to 7 H'F0 H'F0 H'F0 Lower 16 bits of the address. Port 5 Data Direction Register (P5DDR) P5DDR is an 8-bit write-only register that can select input or output for each pin in port 5. Bit Modes Initial value 1 and 3 Read/Write Modes Initial value 5 to 7 Read/Write 7 -- 1 -- 1 -- 6 -- 1 -- 1 -- Reserved bits 5 -- 1 -- 1 -- 4 -- 1 -- 1 -- 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W 0 1 -- 0 W P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR Port 5 data direction 3 to 0 These bits select input or output for port 5 pins P5DDR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P5DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Rev.3.00 Mar. 26, 2007 Page 153 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 5 Data Register (P5DR) P5DR is an 8-bit readable/writable register that stores data for pins P53 to P50. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 P5 3 0 R/W 2 P5 2 0 R/W 1 P5 1 0 R/W 0 P5 0 0 R/W Reserved bits Port 5 data 3 to 0 These bits store data for port 5 pins When a bit in P5DDR is set to 1, if port 5 is read the value of the corresponding P5DR bit is returned directly, regardless of the actual state of the pin. When a bit in P5DDR is cleared to 0, if port 5 is read the corresponding pin level is read. Bits P57 to P54 are reserved. They cannot be modified and are always read as 1. P5DR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Port 5 Input Pull-Up Control Register (P5PCR) P5PCR is an 8-bit readable/writable register that controls the MOS input pull-up transistors in port 5. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR Reserved bits Port 5 input pull-up control 3 to 0 These bits control input pull-up transistors built into port 5 When a P5DDR bit is cleared to 0 (selecting generic input) in modes 5 to 7, if the corresponding bit from P53PCR to P50PCR is set to 1, the input pull-up transistor is turned on. P5PCR is initialized to H'F0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev.3.00 Mar. 26, 2007 Page 154 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.5.3 Pin Functions in Each Mode The pin functions differ between mode 1, 3 (expanded modes with on-chip ROM disabled), mode 5 (expanded modes with on-chip ROM enabled), mode 6, and 7 (single-chip mode). The pin functions in each mode are described below. Modes 1 and 3 Address output can be selected for each pin in port 5. Figure 7.13 shows the pin functions in modes 1 and 3. A 19 (output) Port 5 A 18 (output) A 17 (output) A 16 (output) Figure 7.13 Pin Functions in Modes 1 and 3 (Port 5) Mode 5 Address output or generic input can be selected for each pin in port 5. A pin becomes an address output pin if the corresponding P5DDR bit is set to 1, and a generic input pin if this bit is cleared to 0. Following a reset, all pins are input pins. To use a pin for address output, its P5DDR must be set to 1. Figure 7.14 shows the pin functions in mode 5. When P5DDR = 1 A 19 (output) Port 5 A 18 (output) A 17 (output) A 16 (output) When P5DDR = 0 P5 3 (input) P5 2 (input) P5 1 (input) P5 0 (input) Figure 7.14 Pin Functions in Mode 5 (Port 5) Rev.3.00 Mar. 26, 2007 Page 155 of 682 REJ09B0353-0300 Section 7 I/O Ports Modes 6 and 7 Input or output can be selected separately for each pin in port 5. A pin becomes an output pin if the corresponding P5DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.15 shows the pin functions in modes 6 and 7. P5 3 (input/output) Port 5 P5 2 (input/output) P5 1 (input/output) P5 0 (input/output) Figure 7.15 Pin Functions in Mode 6 and 7 (Port 5) 7.5.4 Input Pull-Up Transistors Port 5 has built-in MOS input pull-up transistors that can be controlled by software. These input pull-up transistors can be turned on and off individually. When a P5PCR bit is set to 1 and the corresponding P5DDR bit is cleared to 0, the input pull-up transistor is turned on. The input pull-up transistors are turned off by a reset and in hardware standby mode. In software standby mode they retain their previous state. Table 7.7 summarizes the states of the input pull-up transistors in each mode. Table 7.7 Mode 1 3 5 6 7 Input Pull-Up Transistor States (Port 5) Hardware Standby Mode Off Off Software Standby Mode Off On/Off Other Modes Off On/Off Reset Off Off Legend: Off: The input pull-up transistor is always off. On/Off: The input pull-up transistor is on if P5PCR = 1 and P5DDR = 0. Otherwise, it is off. Rev.3.00 Mar. 26, 2007 Page 156 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.6 7.6.1 Port 6 Overview Port 6 is a 4-bit input/output port that is also used for input and output of bus control signals (WR, RD, AS, and WAIT). Figure 7.16 shows the pin configuration of port 6. In modes 1, 3 and 5, the pin functions are WR, RD, AS, and P60/WAIT. In modes 6 and 7, port 6 is a generic input/output port. Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. Port 6 pins P6 5 / WR Port 6 P6 4 / RD P6 3 / AS P6 0 / WAIT Modes 1, 3 and 5 WR (output) RD (output) AS (output) P60 (input/output)/WAIT (input) Modes 6 and 7 P6 5 (input/output) P6 4 (input/output) P6 3 (input/output) P6 0 (input/output) Figure 7.16 Port 6 Pin Configuration Rev.3.00 Mar. 26, 2007 Page 157 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.6.2 Register Descriptions Table 7.8 summarizes the registers of port 6. Table 7.8 Port 6 Registers Initial Value Address* H'FFC9 H'FFCB Note: * Name Port 6 data direction register Port 6 data register Abbreviation P6DDR P6DR R/W W R/W Modes 1, 3, and 5 H'F8 H'80 Modes 6 and 7 H'80 H'80 Lower 16 bits of the address. Port 6 Data Direction Register (P6DDR) P6DDR is an 8-bit write-only register that can select input or output for each pin in port 6. Bit Initial value Read/Write 7 -- 1 -- 6 -- 0 W 5 0 W 4 0 W 3 0 W 2 -- 0 W 1 -- 0 W 0 P6 0 DDR 0 W P6 5 DDR P6 4 DDR P6 3 DDR Reserved bits Port 6 data direction 5 to 3, 0 These bits select input or output for port 6 pins Bits 7, 6, 2, and 1 are reserved. P6DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P6DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P6DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Rev.3.00 Mar. 26, 2007 Page 158 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 6 Data Register (P6DR) P6DR is an 8-bit readable/writable register that stores data for pins P65 to P63 and P60. Bit Initial value Read/Write 7 -- 1 -- 6 -- 0 R/W 5 P6 5 0 R/W 4 P6 4 0 R/W 3 P6 3 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 P6 0 0 R/W Reserved bits Port 6 data 5 to 3, 0 These bits store data for port 6 pins When a bit in P6DDR is set to 1, if port 6 is read the value of the corresponding P6DR bit is returned directly. When a bit in P6DDR is cleared to 0, if port 6 is read the corresponding pin level is read. Bits 7, 6, 2, and 1 are reserved. Bit 7 cannot be modified and always reads 1. Bits 6, 2, and 1 can be written and read, but cannot be used as ports. If bit 6, 2, or 1 in P6DDR is read while its value is 1, the value of the corresponding bit in P6DR will be read. If bit 6, 2, or 1 in P6DDR is read while its value is 0, it will always read 1. P6DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev.3.00 Mar. 26, 2007 Page 159 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.6.3 Pin Functions in Each Mode Modes 1, 3, and 5 P65 to P63 function as bus control output pins. P60 is either a bus control input pin or generic input/output pin, functioning as an output pin when bit P60DDR is set to 1 and an input pin when this bit is cleared to 0. Figure 7.17 and table 7.9 indicate the pin functions in modes 1, 3, and 5. WR (output) Port 6 RD (output) AS (output) P60 (input/output)/WAIT (input) Figure 7.17 Pin Functions in Modes 1, 3, and 5 (Port 6) Rev.3.00 Mar. 26, 2007 Page 160 of 682 REJ09B0353-0300 Section 7 I/O Ports Table 7.9 Pin P65/WR Port 6 Pin Functions in Modes 1, 3, and 5 Pin Functions and Selection Method Functions as follows regardless of P65DDR P65DDR Pin function 0 WR output 1 P64/RD Functions as follows regardless of P64DDR P64DDR Pin function 0 RD output 1 P63/AS Functions as follows regardless of P63DDR P63DDR Pin function 0 AS output 1 P60/WAIT Bits WCE7 to WCE0 in WCER, bit WMS1 in WCR, and bit P60DDR select the pin function as follows WCER WMS1 P60DDR Pin function Note: * 0 P60 input Do not set bit P60DDR to 1. 0 1 P60 output All 1s 1 0* Not all 1s -- 0* WAIT input Rev.3.00 Mar. 26, 2007 Page 161 of 682 REJ09B0353-0300 Section 7 I/O Ports Modes 6 and 7 Input or output can be selected separately for each pin in port 6. A pin becomes an output pin if the corresponding P6DDR bit is set to 1, and an input pin if this bit is cleared to 0. Figure 7.18 shows the pin functions in modes 6 and 7. P6 5 (input/output) Port 6 P6 4 (input/output) P6 3 (input/output) P6 0 (input/output) Figure 7.18 Pin Functions in Modes 6 and 7 (Port 6) Rev.3.00 Mar. 26, 2007 Page 162 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.7 7.7.1 Port 7 Overview Port 7 is an 8-bit input port that is also used for analog input to the A/D converter. The pin functions are the same in all operating modes. Figure 7.19 shows the pin configuration of port 7. Port 7 pins P77 (input)/AN 7 (input) P76 (input)/AN 6 (input) P75 (input)/AN 5 (input) Port 7 P74 (input)/AN 4 (input) P73 (input)/AN 3 (input) P72 (input)/AN 2 (input) P71 (input)/AN 1 (input) P70 (input)/AN 0 (input) Figure 7.19 Port 7 Pin Configuration 7.7.2 Register Description Table 7.10 summarizes the port 7 register. Port 7 is an input-only port, so it has no data direction register. Table 7.10 Port 7 Data Register Address* H'FFCE Note: * Name Port 7 data register Lower 16 bits of the address. Abbreviation P7DR R/W R Initial Value Undetermined Rev.3.00 Mar. 26, 2007 Page 163 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 7 Data Register (P7DR) Bit Initial value Read/Write 7 P77 --* R 6 P76 --* R 5 P75 --* R 4 P74 --* R 3 P73 --* R 2 P72 --* R 1 P71 --* R 0 P70 --* R Note: * Determined by pins P7 to P0. When P7DR is read, the pin levels are always read. 7.8 7.8.1 Port 8 Overview Port 8 is a 2-bit input/output port that is also used for IRQ1 and IRQ0 input. Figure 7.20 shows the pin configuration of port 8. Pin P80 functions as input/output pin or as an IRQ0 input pin. Pins P81 function as either input pins or IRQ1 input pins in modes 1, 3, and 5, and as input/output pins or IRQ1 input pins in modes 6 and 7. Pins in port 8 can drive one TTL load and a 90-pF capacitive load. They can also drive a Darlington transistor pair. Pins P81 and P80 have Schmitt-trigger inputs. Port 8 pins Modes 1, 3, and 5 Modes 6 and 7 Port 8 P81/IRQ1 P80/IRQ0 P81 (input)/IRQ1 (input) P81 (input/output)/IRQ1 (input) P80 (input/output)/IRQ0 (input) P80 (input/output)/IRQ0 (input) Figure 7.20 Port 8 Pin Configuration Rev.3.00 Mar. 26, 2007 Page 164 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.8.2 Register Descriptions Table 7.11 summarizes the registers of port 8. Table 7.11 Port 8 Registers Address* H'FFCD H'FFCF Note: * Name Port 8 data direction register Port 8 data register Lower 16 bits of the address. Abbreviation P8DDR P8DR R/W W R/W Initial Value H'E0 H'E0 Port 8 Data Direction Register (P8DDR) P8DDR is an 8-bit write-only register that can select input or output for each pin in port 8. 7 Bit Initial value Read/Write -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 W 3 -- 0 W 2 -- 0 W 1 0 W 0 0 W P8 1 DDR P8 0 DDR Reserved bits Port 8 data direction 1 and 0 These bits select input or output for port 8 pins P8DDR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P8DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Rev.3.00 Mar. 26, 2007 Page 165 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 8 Data Register (P8DR) P8DR is an 8-bit readable/writable register that stores data for pins P81 to P80. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 R/W 3 -- 0 R/W 2 -- 0 R/W 1 P8 1 0 R/W 0 P8 0 0 R/W Reserved bits Port 8 data 1 and 0 These bits store data for port 8 pins When a bit in P8DDR is set to 1, if port 8 is read the value of the corresponding P8DR bit is returned directly. When a bit in P8DDR is cleared to 0, if port 8 is read the corresponding pin level is read. Bits 7 to 2 are reserved. Bits 7 to 5 cannot be modified and always read 1. Bit 4, 3, and 2 can be written and read, but it cannot be used for port input or output. If bit 4, 3, and 2 of P8DDR is read while its value is 1, bit 4, 3 and 2 of P8DR is read directly. If bit 4, 3, and 2 of P8DDR is read while its value is 0, it always reads 1. P8DR is initialized to H'E0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. Rev.3.00 Mar. 26, 2007 Page 166 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.8.3 Pin Functions The port 8 pins are also used for IRQ1 and IRQ0. Table 7.12 describes the selection of pin functions. Table 7.12 Port 8 Pin Functions Pin P81/IRQ1 Pin Functions and Selection Method Bit P81DDR selects the pin function as follows P81DDR Pin function 0 Modes 1, 3, and 5 P81 input Illegal setting IRQ1 input P80/IRQ0 Bit P80DDR selects the pin function as follows P80DDR Pin function 0 P80 input IRQ0 input 1 P80 output 1 Modes 6 and 7 P81 output Rev.3.00 Mar. 26, 2007 Page 167 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.9 7.9.1 Port 9 Overview Port 9 is a 6-bit input/output port that is also used for input and output (TxD0, TxD1, RxD0, RxD1, SCK0, SCK1) by serial communication interface channels 0 and 1 (SCI0 and SCI1), and for IRQ5 and IRQ4 input. Port 9 has the same set of pin functions in all operating modes. Figure 7.21 shows the pin configuration of port 9. Pins in port 9 can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington transistor pair. Port 9 pins P95 (input/output)/SCK 1 (input/output)/IRQ 5 (input) P94 (input/output)/SCK 0 (input/output)/IRQ 4 (input) Port 9 P93 (input/output)/RxD1 (input) P92 (input/output)/RxD0 (input) P91 (input/output)/TxD1 (output) P90 (input/output)/TxD0 (output) Figure 7.21 Port 9 Pin Configuration 7.9.2 Register Descriptions Table 7.13 summarizes the registers of port 9. Table 7.13 Port 9 Registers Address* H'FFD0 H'FFD2 Note: * Name Port 9 data direction register Port 9 data register Lower 16 bits of the address. Abbreviation P9DDR P9DR R/W W R/W Initial Value H'C0 H'C0 Rev.3.00 Mar. 26, 2007 Page 168 of 682 REJ09B0353-0300 Section 7 I/O Ports Port 9 Data Direction Register (P9DDR) P9DDR is an 8-bit write-only register that can select input or output for each pin in port 9. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P9 5 DDR P9 4 DDR P9 3 DDR P9 2 DDR P9 1 DDR P9 0 DDR Reserved bits Port 9 data direction 5 to 0 These bits select input or output for port 9 pins A pin in port 9 becomes an output pin if the corresponding P9DDR bit is set to 1, and an input pin if this bit is cleared to 0. P9DDR is a write-only register. Its value cannot be read. All bits return 1 when read. P9DDR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a P9DDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port 9 Data Register (P9DR) P9DR is an 8-bit readable/writable register that stores output data for pins P95 to P90. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 P9 5 0 R/W 4 P9 4 0 R/W 3 P9 3 0 R/W 2 P9 2 0 R/W 1 P9 1 0 R/W 0 P9 0 0 R/W Reserved bits Port 9 data 5 to 0 These bits store data for port 9 pins When a bit in P9DDR is set to 1, if port 9 is read the value of the corresponding P9DR bit is returned. When a bit in P9DDR is cleared to 0, if port 9 is read the corresponding pin level is read. Bits 7 and 6 are reserved. They cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 169 of 682 REJ09B0353-0300 Section 7 I/O Ports P9DR is initialized to H'C0 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. 7.9.3 Pin Functions The port 9 pins are also used for SCI input and output (TxD, RxD, SCK), and for IRQ5 and IRQ4 input. Table 7.14 describes the selection of pin functions. Table 7.14 Port 9 Pin Functions Pin P95/SCK1/ IRQ5 Pin Functions and Selection Method Bit C/A in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P95DDR select the pin function as follows CKE1 C/A CKE0 P95DDR Pin function 0 P95 input 0 1 P95 output 0 1 -- SCK1 output 0 1 -- -- SCK1 output 1 -- -- -- SCK1 input IRQ5 input P94/SCK0/ IRQ4 Bit C/A in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI, and bit P94DDR select the pin function as follows CKE1 C/A CKE0 P94DDR Pin function 0 P94 input 0 1 P94 output 0 1 -- SCK0 output 0 1 -- -- SCK0 output 1 -- -- -- SCK0 input IRQ4 input Rev.3.00 Mar. 26, 2007 Page 170 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin P93/RxD1 Pin Functions and Selection Method Bit RE in SCR of SCI1 and bit P93DDR select the pin function as follows RE P93DDR Pin function 0 P93 input 0 1 P93 output 1 -- RxD1 input P92/RxD0 Bit RE in SCR of SCI0, bit SMIF in SCMR, and bit P92DDR select the pin function as follows SMIF RE P92DDR Pin function 0 P92 input 0 1 P92 output 0 1 -- RxD0 input 1 -- -- RxD0 input P91/TxD1 Bit TE in SCR of SCI1 and bit P91DDR select the pin function as follows TE P91DDR Pin function 0 P91 input 0 1 P91 output 1 -- TxD1 output P90/TxD0 Bit TE in SCR of SCI0, bit SMIF in SCMR, and bit P90DDR select the pin function as follows SMIF TE P90DDR Pin function Note: * 0 P90 input 0 1 P90 output 0 1 -- TxD0 output 1 -- -- TxD0 output* Functions as the TxD0 output pin, but there are two states: one in which the pin is driven, and another in which the pin is at high impedance. Rev.3.00 Mar. 26, 2007 Page 171 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.10 7.10.1 Port A Overview Port A is an 8-bit input/output port that is also used for output (TP7 to TP0) from the programmable timing pattern controller (TPC), input and output (TIOCB2, TIOCA2, TIOCB1, TIOCA1, TIOCB0, TIOCA0, TCLKD, TCLKC, TCLKB, TCLKA) by the 16-bit integrated timer unit (ITU), and address output (A23 to A20). Figure 7.22 shows the pin configuration of port A. Pins in port A can drive one TTL load and a 30-pF capacitive load. They can also drive a Darlington transistor pair. Port A has Schmitt-trigger inputs. Port A pins PA7 /TP7/TIOCB 2 /A 20 PA6 /TP6/TIOCA 2 /A 21 PA5 /TP5/TIOCB 1 /A 22 PA4 /TP4/TIOCA 1 /A 23 Port A PA3 /TP3/TIOCB 0 /TCLKD PA2 /TP2/TIOCA 0 /TCLKC PA1 /TP1/TCLKB PA0 /TP0/TCLKA Modes 1, 5 and 7 PA 7 (input/output)/TP7 (output)/TIOCB 2 (input/output) PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output) PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output) PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output) PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP1 (output)/TCLKB (input) PA 0 (input/output)/TP0 (output)/TCLKA (input) Mode 3 A 20 (output) PA 6 (input/output)/TP6 (output)/TIOCA 2 (input/output) /A 21 (output) PA 5 (input/output)/TP5 (output)/TIOCB 1 (input/output) /A 22 (output) PA 4 (input/output)/TP4 (output)/TIOCA 1 (input/output) /A 23 (output) PA 3 (input/output)/TP3 (output)/TIOCB 0 (input/output)/TCLKD (input) PA 2 (input/output)/TP2 (output)/TIOCA 0 (input/output)/TCLKC (input) PA 1 (input/output)/TP1 (output)/TCLKB (input) PA 0 (input/output)/TP0 (output)/TCLKA (input) Figure 7.22 Port A Pin Configuration Rev.3.00 Mar. 26, 2007 Page 172 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.10.2 Register Descriptions Table 7.15 summarizes the registers of port A. Table 7.15 Port A Registers Initial Value Address* H'FFD1 H'FFD3 Note: * Name Port A data direction register Port A data register Abbreviation PADDR PADR R/W W R/W Modes 1, 5, and 7 H'00 H'00 Mode 3 H'80 H'00 Lower 16 bits of the address. Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that can select input or output for each pin in port A. The corresponding PADDR bit should also be set when a pin is used as a TPC output. 7 Bit Modes 1, 5, and 7 Mode 3 Initial value Read/Write Initial value Read/Write 0 W 1 -- 6 0 W 0 W 5 0 W 0 W 4 0 W 0 W 3 0 W 0 W 2 0 W 0 W 1 0 W 0 W 0 0 W 0 W PA7 DDR PA6 DDR PA5 DDR PA4 DDR PA3 DDR PA2 DDR PA1 DDR PA0 DDR Port A data direction 7 to 0 These bits select input or output for port A pins A pin in port A becomes an output pin if the corresponding PADDR bit is set to 1, and an input pin if this bit is cleared to 0. However, in mode 3, PA7 DDR is fixed at 1, and PA7 functions as an address output pin. PADDR is a write-only register. Its value cannot be read. All bits return 1 when read. PADDR is initialized to H'00 in modes 1, 5 and 7 and to H'80 in mode 3 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a PADDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Rev.3.00 Mar. 26, 2007 Page 173 of 682 REJ09B0353-0300 Section 7 I/O Ports Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores data for pins PA7 to PA0. Bit Initial value Read/Write 7 PA 7 0 R/W 6 PA 6 0 R/W 5 PA 5 0 R/W 4 PA 4 0 R/W 3 PA 3 0 R/W 2 PA 2 0 R/W 1 PA 1 0 R/W 0 PA 0 0 R/W Port A data 7 to 0 These bits store data for port A pins When a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned directly. When a bit in PADDR is cleared to 0, if port A is read the corresponding pin level is read. PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. When port A pins are used for TPC output, PADR stores output data for TPC output groups 0 and 1. If a bit in the next data enable register (NDERA) is set to 1, the corresponding PADR bit cannot be written. In this case, PADR can be updated only when data is transferred from NDRA. Rev.3.00 Mar. 26, 2007 Page 174 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.10.3 Pin Functions The port A pins are also used for TPC output (TP7 to TP0), ITU input/output (TIOCB2 to TIOCB0, TIOCA2 to TIOCA0) and input (TCLKD, TCLKC, TCLKB, TCLKA), and as address bus pins (A23 to A20). Table 7.16 describes the selection of pin functions. Table 7.16 Port A Pin Functions Pin PA7/TP7/ TIOCB2/ A20 Pin Functions and Selection Method The mode setting, ITU channel 2 settings (bit PWM2 in TMDR and bits IOB2 to IOB0 in TIOR2), bit NDER7 in NDERA, and bit PA7DDR in PADDR select the pin function as follows Mode ITU channel 2 settings PA7DDR NDER7 Pin function (1) in table below -- -- TIOCB2 output 0 -- PA7 input 1, 5 to 7 (2) in table below -- 1 0 PA7 output 1 1 TP7 output -- -- A20 output 3 TIOCB2 input* Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. (2) 0 0 0 0 1 1 -- (1) (2) 1 -- -- ITU channel 2 settings IOB2 IOB1 IOB0 Rev.3.00 Mar. 26, 2007 Page 175 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PA6/TP6/ TIOCA2/ A21 Pin Functions and Selection Method The mode setting, bit A21E in BRCR, ITU channel 2 settings (bit PWM2 in TMDR and bits IOA2 to IOA0 in TIOR2), bit NDER6 in NDERA, and bit PA6DDR in PADDR select the pin function as follows Mode A21E ITU channel 2 settings PA6DDR NDER6 Pin function Note: * (1) in table below -- -- TIOCA2 output 1, 5 to 7 -- (2) in table below (1) in table below -- -- 1 (2) in table below -- 0 -- PA6 input 1 0 1 1 -- -- 3 0 0 -- PA6 input 1 0 PA6 output 1 1 TP6 TIOCA2 output output PA6 TP6 A21 output output output TIOCA2 input* TIOCA2 input when IOA2 = 1. (2) (1) 0 0 0 0 0 1 1 -- 1 -- -- (2) ITU channel 2 settings PWM2 IOA2 IOA1 IOA0 TIOCA2 input* (1) 1 -- -- -- Rev.3.00 Mar. 26, 2007 Page 176 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PA5/TP5/ TIOCB1/ A22 Pin Functions and Selection Method The mode setting, bit A22E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and bits IOB2 to IOB0 in TIOR1), bit NDER5 in NDERA, and bit PA5DDR in PADDR select the pin function as follows Mode A22E ITU channel 1 settings PA5DDR NDER5 Pin function Note: * (1) in table below -- -- TIOCB1 output 1, 5 to 7 -- (2) in table below (1) in table below -- -- 1 (2) in table below 3 0 -- 0 -- PA5 input 1 0 PA5 output 1 1 0 -- PA5 input 1 0 1 1 -- -- TP5 TIOCB1 output output PA5 TP5 A22 output output output TIOCB1 input* TIOCB1 input when IOB2 = 1 and PWM1 = 0. (2) 0 0 0 0 1 1 -- (1) TIOCB1 input* ITU channel 1 settings IOB2 IOB1 IOB0 (2) 1 -- -- Rev.3.00 Mar. 26, 2007 Page 177 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PA4/TP4/ TIOCB1/ A23 Pin Functions and Selection Method The mode setting, bit A23E in BRCR, ITU channel 1 settings (bit PWM1 in TMDR and bits IOA2 to IOA0 in TIOR1), bit NDER4 in NDERA, and bit PA4DDR in PADDR select the pin function as follows Mode A23E ITU channel 1 settings PA4DDR NDER4 Pin function Note: * (1) in table below -- -- TIOCA1 output 1, 5 to 7 -- (2) in table below (1) in table below -- -- 1 (2) in table below 3 0 -- 0 -- PA4 input 1 0 PA4 output 1 1 0 -- 1 0 1 1 -- -- TP5 TIOCA1 PA4 output output input PA4 TP4 A23 output output output TIOCA1 input* TIOCA1 input when IOA2 = 1. (2) (1) 0 0 0 0 0 1 1 -- 1 -- -- (2) ITU channel 1 settings PWM1 IOA2 IOA1 IOA0 TIOCA1 input* (1) 1 -- -- -- Rev.3.00 Mar. 26, 2007 Page 178 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PA3/TP3/ TIOCB0/ TCLKD Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOB2 to IOB0 in TIOR0), bits TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER3 in NDERA, and bit PA3DDR in PADDR select the pin function as follows ITU channel 0 settings PA3DDR NDER3 Pin function (1) in table below (2) in table below -- -- TIOCB0 output 0 -- PA3 input TCLKD input* 2 1 0 1 1 1 PA3 output TP3 output TIOCB0 input* Notes: 1. TIOCB0 input when IOB2 = 1 and PWM0 = 0. 2. TCLKD input when TPSC2 = TPSC1 = TPSC0 = 1 in any of TCR4 to TCR0. ITU channel 0 settings IOB2 IOB1 IOB0 0 0 (2) 0 0 1 1 -- (1) (2) 1 -- -- Rev.3.00 Mar. 26, 2007 Page 179 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PA2/TP2/ TIOCA0/ TCLKC Pin Functions and Selection Method ITU channel 0 settings (bit PWM0 in TMDR and bits IOA2 to IOA0 in TIOR0), bits TPSC2 to TPSC0 in TCR4 to TCR0, bit NDER2 in NDERA, and bit PA2DDR in PADDR select the pin function as follows ITU channel 0 settings PA2DDR NDER2 Pin function (1) in table below (2) in table below -- -- TIOCA0 output 0 -- 1 0 1 1 1 PA2 input PA2 output TP2 output TIOCA0 input* TCLKC input* 2 Notes: 1. TIOCA0 input when IOA2 = 1. 2. TCLKC input when TPSC2 = TPSC1 = 1 and TPSC0 = 0 in any of TCR4 to TCR0. ITU channel 0 settings PWM0 IOA2 IOA1 IOA0 0 0 0 0 1 1 -- (2) (1) 0 1 -- -- (2) (1) 1 -- -- -- Rev.3.00 Mar. 26, 2007 Page 180 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PA1/TP1/ TCLKB Pin Functions and Selection Method Bit NDER1 in NDERA and bit PA1DDR in PADDR select the pin function as follows PA1DDR NDER1 Pin function Note: * 0 -- PA1 input 1 0 PA1 output TCLKB input* TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0. 1 1 TP1 output PA0/TP0/ TCLKA Bit NDER0 in NDERA and bit PA0DDR in PADDR select the pin function as follows PA0DDR NDER0 Pin function Note: * 0 -- PA0 input 1 0 PA0 output TCLKA input* TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 = TPSC0 = 0 in any of TCR4 to TCR0. 1 1 TP0 output Rev.3.00 Mar. 26, 2007 Page 181 of 682 REJ09B0353-0300 Section 7 I/O Ports 7.11 7.11.1 Port B Overview Port B is a 7-bit input/output port that is also used for TPC output (TP15, TP13 to TP8), ITU input/output (TIOCB4, TIOCB3, TIOCA4, TIOCA3) and ITU output (TOCXB4, TOCXA4), and ADTRG input to the A/D converter. Port B has the same set of pin functions in all operating modes. Figure 7.23 shows the pin configuration of port B. Pins in port B can drive one TTL load and a 30-pF capacitive load. They can also drive an LED or a Darlington transistor pair. Pins PB3 to PB0 have Schmitt-trigger inputs. Port B pins PB 7 (input/output)/TP15 (output)/ADTRG (input) PB 5 (input/output)/TP13 (output)/TOCXB 4 (output) PB 4 (input/output)/TP12 (output)/TOCXA 4 (output) Port B PB 3 (input/output)/TP11 (output)/TIOCB 4 (input/output) PB 2 (input/output)/TP10 (output)/TIOCA 4 (input/output) PB 1 (input/output)/TP9 (output)/TIOCB 3 (input/output) PB 0 (input/output)/TP8 (output)/TIOCA 3 (input/output) Figure 7.23 Port B Pin Configuration 7.11.2 Register Descriptions Table 7.17 summarizes the registers of port B. Table 7.17 Port B Registers Address* H'FFD4 H'FFD6 Note: * Name Port B data direction register Port B data register Lower 16 bits of the address. Abbreviation PBDDR PBDR R/W W R/W Initial Value H'00 H'00 Rev.3.00 Mar. 26, 2007 Page 182 of 682 REJ09B0353-0300 Section 7 I/O Ports Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that can select input or output for each pin in port B. Bit Initial value Read/Write 7 PB7 DDR 0 W 6 -- 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Reserved bit Port B data 7, 5 to 0 These bits select input or output for port B pins A pin in port B becomes an output pin if the corresponding PBDDR bit is set to 1, and an input pin if this bit is cleared to 0. Bit 6 is reserved. PBDDR is a write-only register. Its value cannot be read. All bits return 1 when read. PBDDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. If a PBDDR bit is set to 1, the corresponding pin maintains its output state in software standby mode. Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores data for pins PB7, PB5 to PB0. Bit Initial value Read/Write 7 PB 7 0 R/W 6 -- 0 R/W 5 PB 5 0 R/W 4 PB 4 0 R/W 3 PB 3 0 R/W 2 PB 2 0 R/W 1 PB 1 0 R/W 0 PB 0 0 R/W Reserved bit Port B data 7, 5 to 0 These bits store data for port B pins When a bit in PBDDR is set to 1, if port B is read the value of the corresponding PBDR bit is returned directly. When a bit in PBDDR is cleared to 0, if port B is read the corresponding pin level is read. Bit 6 is reserved. Bit 6 can be written and read, but cannot be used for a port input or output. Rev.3.00 Mar. 26, 2007 Page 183 of 682 REJ09B0353-0300 Section 7 I/O Ports If bit 6 in PBDDR is read while its value is 1, the value of bit 6 in PBDR will be read directly. If bit 6 in PBDDR is read while its value is 0, it will always be read as 1. PBDR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it retains its previous setting. When port B pins are used for TPC output, PBDR stores output data for TPC output groups 2 and 3. If a bit in the next data enable register (NDERB) is set to 1, the corresponding PBDR bit cannot be written. In this case, PBDR can be updated only when data is transferred from NDRB. 7.11.3 Pin Functions The port B pins are also used for TPC output (TP15, TP13 to TP8), ITU input/output (TIOCB4, TIOCB3, TIOCA4, TIOCA3) and output (TOCXB4, TOCXA4), and ADTRG input. Table 7.18 describes the selection of pin functions. Rev.3.00 Mar. 26, 2007 Page 184 of 682 REJ09B0353-0300 Section 7 I/O Ports Table 7.18 Port B Pin Functions Pin PB7/ TP15/ ADTRG Pin Functions and Selection Method Bit TRGE in ADCR, bit NDER15 in NDERB and bit PB7DDR in PBDDR select the pin function as follows PB7DDR NDER15 Pin function Notes: * 0 -- PB7 input 1 0 PB7 output ADTRG input* ADTRG input when TRGE = 1. 1 1 TP15 output PB5/ TP13/ TOCXB4 ITU channel 4 settings (bit CMD1 in TFCR and bit EXB4 in TOER), bit NDER13 in NDERB, and bit PB5DDR in PBDDR select the pin function as follows EXB4, CMD1 PB5DDR NDER13 Pin function 0 -- PB5 input Not both 1 1 0 PB5 output 1 1 TP13 output Both 1 -- -- TOCXB4 output PB4/ TP12/ TOCXA4 ITU channel 4 settings (bit CMD1 in TFCR and bit EXA4 in TOER), bit NDER12 in NDERB, and bit PB4DDR in PBDDR select the pin function as follows EXA4, CMD1 PB4DDR NDER12 Pin function 0 -- PB4 input Not both 1 1 0 PB4 output 1 1 TP12 output Both 1 -- -- TOCXA4 output Rev.3.00 Mar. 26, 2007 Page 185 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PB3/ TP11/ TIOCB4 Pin Functions and Selection Method ITU channel 4 settings (bit PWM4 in TMDR, bit CMD1 in TFCR, bit EB4 in TOER, and bits IOB2 to IOB0 in TIOR4), bit NDER11 in NDERB, and bit PB3DDR in PBDDR select the pin function as follows ITU channel 4 settings PB3DDR NDER11 Pin function Note: * (1) in table below -- -- TIOCB4 output 0 -- PB3 input (2) in table below 1 0 PB3 output TIOCB4 input* TIOCB4 input when CMD1 = PWM4 = 0 and IOB2 = 1. (2) 0 -- -- -- -- 0 0 0 0 0 1 0 0 1 -- 1 -- -- (2) (1) 1 1 -- -- -- (2) (1) ITU channel 4 settings EB4 CMD1 IOB2 IOB1 IOB0 1 1 TP11 output Rev.3.00 Mar. 26, 2007 Page 186 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PB2/ TP10/ TIOCA4 Pin Functions and Selection Method ITU channel 4 settings (bit CMD1 in TFCR, bit EA4 in TOER, bit PWM4 in TMDR, and bits IOA2 to IOA0 in TIOR4), bit NDER10 in NDERB, and bit PB2DDR in PBDDR select the pin function as follows ITU channel 4 settings PB2DDR NDER11 Pin function Note: * (1) in table below -- -- TIOCA4 output 0 -- PB2 input (2) in table below 1 0 1 1 PB2 output TP10 output TIOCA4 input* TIOCA4 input when CMD1 = PWM4 = 0 and IOB2 = 1. (2) 0 -- -- -- -- -- 0 0 0 0 0 1 0 0 1 -- 1 -- -- 0 1 -- -- -- (2) (1) 1 1 -- -- -- -- (2) (1) ITU channel 4 settings EA4 CMD1 PWM4 IOA2 IOA1 IOA0 Rev.3.00 Mar. 26, 2007 Page 187 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PB1/TP9/ TIOCB3 Pin Functions and Selection Method ITU channel 3 settings (bit PWM3 in TMDR, bit CMD1 in TFCR, bit EB3 in TOER, and bits IOB2 to IOB0 in TIOR3), bit NDER11 in NDERB, and bit PB1DDR in PBDDR select the pin function as follows ITU channel 3 settings PB1DDR NDER9 Pin function Note: * (1) in table below -- -- TIOCB3 output 0 -- PB1 input (2) in table below 1 0 PB1 output TIOCB3 input* TIOCB3 input when CMD1 = PWM3 = 0 and IOB2 = 1. (2) 0 -- -- -- -- 0 0 0 0 0 1 0 0 1 -- 1 -- -- (2) (1) 1 1 -- -- -- (2) (1) ITU channel 3 settings EB3 CMD1 IOB2 IOB1 IOB0 1 1 TP9 output Rev.3.00 Mar. 26, 2007 Page 188 of 682 REJ09B0353-0300 Section 7 I/O Ports Pin PB0/TP8/ TIOCA3 Pin Functions and Selection Method ITU channel 3 settings (bit CMD1 in TFCR, bit EA3 in TOER, bit PWM3 in TMDR, and bits IOA2 to IOA0 in TIOR3), bit NDER8 in NDERB, and bit PB0DDR in PBDDR select the pin function as follows ITU channel 3 settings PB0DDR NDER8 Pin function Note: * (1) in table below -- -- TIOCA3 output 0 -- PB0 input (2) in table below 1 0 PB0 output TIOCA3 input* TIOCA3 input when CMD1 = PWM3 = 0 and IOA2 = 1. (2) 0 -- -- -- -- -- 0 0 0 0 0 1 0 0 1 -- 1 -- -- 0 1 -- -- -- (2) (1) 1 1 -- -- -- -- (2) (1) ITU channel 3 settings EA3 CMD1 PWM3 IOA2 IOA1 IOA0 1 1 TP8 output Rev.3.00 Mar. 26, 2007 Page 189 of 682 REJ09B0353-0300 Section 7 I/O Ports Rev.3.00 Mar. 26, 2007 Page 190 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Section 8 16-Bit Integrated Timer Unit (ITU) 8.1 Overview The H8/3039 Group has a built-in 16-bit integrated timer-pulse unit (ITU) with five 16-bit timer channels. 8.1.1 Features ITU features are listed below. * Capability to process up to 12 pulse outputs or 10 pulse inputs * Ten general registers (GRs, two per channel) with independently-assignable output compare or input capture functions * Selection of eight counter clock sources for each channel: Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD * Five operating modes selectable in all channels: Waveform output by compare match Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2) Input capture function Rising edge, falling edge, or both edges (selectable) Counter clearing function Counters can be cleared by compare match or input capture Synchronization Two or more timer counters (TCNTs) can be preset simultaneously, or cleared simultaneously by compare match or input capture. Counter synchronization enables synchronous register input and output. PWM mode PWM output can be provided with an arbitrary duty cycle. With synchronization, up to five-phase PWM output is possible * Phase counting mode selectable in channel 2 Two-phase encoder output can be counted automatically. Rev.3.00 Mar. 26, 2007 Page 191 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) * Three additional modes selectable in channels 3 and 4 Reset-synchronized PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of complementary waveforms. Complementary PWM mode If channels 3 and 4 are combined, three-phase PWM output is possible with three pairs of non-overlapping complementary waveforms. Buffering Input capture registers can be double-buffered. Output compare registers can be updated automatically. * High-speed access via internal 16-bit bus The 16-bit timer counters, general registers, and buffer registers can be accessed at high speed via a 16-bit bus. * Fifteen interrupt sources Each channel has two compare match/input capture interrupts and an overflow interrupt. All interrupts can be requested independently. * Output triggering of programmable pattern controller (TPC) Compare match/input capture signals from channels 0 to 3 can be used as TPC output triggers. Table 8.1 summarizes the ITU functions. Rev.3.00 Mar. 26, 2007 Page 192 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.1 Item Clock sources ITU Functions Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Internal clocks: , /2, /4, /8 External clocks: TCLKA, TCLKB, TCLKC, TCLKD, selectable independently GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 General registers GRA0, GRB0 (output compare/ input capture registers) Buffer registers Input/output pins Output pins Counter clearing function Compare match output 0 1 Toggle Input capture function Synchronization PWM mode Reset-synchronized PWM mode Complementary PWM mode Phase counting mode Buffering Interrupt sources -- -- -- BRA3, BRB3 BRA4, BRB4 TIOCA0, TIOCB0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3 TIOCA4, TIOCB4 -- -- -- -- TOCXA4, TOCXB4 GRA4/GRB4 GRA3/GRB3 GRA2/GRB2 GRA1/GRB1 GRA0/GRB0 compare match compare match compare match compare match compare match or input capture or input capture or input capture or input capture or input capture O O O O O O -- -- -- -- Three sources * Compare match/input capture A0 * Compare match/input capture B0 * Overflow O O O O O O -- -- -- -- Three sources * Compare match/input capture A1 * Compare match/input capture B1 * Overflow O O -- O O O -- -- O -- Three sources * Compare match/input capture A2 * Compare match/input capture B2 * Overflow O O O O O O O O -- O Three sources * Compare match/input capture A3 * Compare match/input capture B3 * Overflow O O O O O O O O -- O Three sources * Compare match/input capture A4 * Compare match/input capture B4 * Overflow Legend: O: Available --: Not available Rev.3.00 Mar. 26, 2007 Page 193 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.1.2 Block Diagrams ITU Block Diagram (Overall) Figure 8.1 is a block diagram of the ITU. TCLKA to TCLKD , /2, /4, /8 TOCXA4, TOCXB4 TIOCA0 to TIOCA4 TIOCB0 to TIOCB4 Clock selector IMIA0 to IMIA4 IMIB0 to IMIB4 OVI0 to OVI4 Control logic TOER 16-bit timer channel 4 16-bit timer channel 3 16-bit timer channel 2 16-bit timer channel 1 16-bit timer channel 0 TOCR TSTR TSNC TMDR TFCR Module data bus Legend: TOER: Timer output master enable register (8 bits) TOCR: Timer output control register (8 bits) TSTR: Timer start register (8 bits) TSNC: Timer synchro register (8 bits) TMDR: Timer mode register (8 bits) TFCR: Timer function control register (8 bits) Figure 8.1 ITU Block Diagram (Overall) Rev.3.00 Mar. 26, 2007 Page 194 of 682 REJ09B0353-0300 Internal data bus Bus interface Section 8 16-Bit Integrated Timer Unit (ITU) Block Diagram of Channels 0 and 1 ITU channels 0 and 1 are functionally identical. Both have the structure shown in figure 8.2. TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic Comparator TIOCA0 TIOCB0 IMIA0 IMIB0 OVI0 TCNT TIOR TIER GRA GRB TCR Module data bus Legend: TCNT: GRA, GRB: TCR: TIOR: TIER: TSR: Timer counter (16 bits) General registers A and B (input capture/output compare registers) (16 bits x 2) Timer control register (8 bits) Timer I/O control register (8 bits) Timer interrupt enable register (8 bits) Timer status register (8 bits) Figure 8.2 Block Diagram of Channels 0 and 1 (for Channel 0) Rev.3.00 Mar. 26, 2007 Page 195 of 682 REJ09B0353-0300 TSR Section 8 16-Bit Integrated Timer Unit (ITU) Block Diagram of Channel 2 Figure 8.3 is a block diagram of channel 2. This is the channel that provides only 0 output and 1 output. TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic Comparator TIOCA2 TIOCB2 IMIA2 IMIB2 OVI2 TCNT2 TIOR2 TIER2 GRA2 GRB2 TCR2 Module data bus Legend: Timer counter 2 (16 bits) TCNT2: GRA2, GRB2: General registers A2 and B2 (input capture/output compare registers) (16 bits x 2) Timer control register 2 (8 bits) TCR2: Timer I/O control register 2 (8 bits) TIOR2: Timer interrupt enable register 2 (8 bits) TIER2: Timer status register 2 (8 bits) TSR2: Figure 8.3 Block Diagram of Channel 2 Rev.3.00 Mar. 26, 2007 Page 196 of 682 REJ09B0353-0300 TSR2 Section 8 16-Bit Integrated Timer Unit (ITU) Block Diagrams of Channels 3 and 4 Figure 8.4 is a block diagram of channel 3. Figure 8.5 is a block diagram of channel 4. TIOCA3 TIOCB3 Control logic Comparator IMIA3 IMIB3 OVI3 TCLKA to TCLKD , /2, /4, /8 Clock selector TCNT3 TIOR3 TIER3 GRA3 GRB3 BRA3 BRB3 TCR3 Module data bus Legend: Timer counter 3 (16 bits) TCNT3: GRA3, GRB3: General registers A3 and B3 (input capture/output compare registers) (16 bits x 2) BRA3, BRB3: Buffer registers A3 and B3 (input capture/output compare buffer registers) (16 bits x 2) Timer control register 3 (8 bits) TCR3: TIOR3: Timer I/O control register 3 (8 bits) TIER3: Timer interrupt enable register 3 (8 bits) TSR3: Timer status register 3 (8 bits) Figure 8.4 Block Diagram of Channel 3 Rev.3.00 Mar. 26, 2007 Page 197 of 682 REJ09B0353-0300 TSR3 Section 8 16-Bit Integrated Timer Unit (ITU) TCLKA to TCLKD , /2, /4, /8 Clock selector Control logic Comparator TOCXA4 TOCXB4 TIOCA4 TIOCB4 IMIA4 IMIB4 OVI4 TCNT4 TIOR4 TIER4 GRA4 GRB4 BRA4 BRB4 TCR4 Module data bus Legend: Timer counter 4 (16 bits) TCNT4: GRA4, GRB4: General registers A4 and B4 (input capture/output compare registers) (16 bits x 2) BRA4, BRB4: Buffer registers A4 and B4 (input capture/output compare buffer registers) (16 bits x 2) Timer control register 4 (8 bits) TCR4: TIOR4: Timer I/O control register 4 (8 bits) TIER4: Timer interrupt enable register 4 (8 bits) TSR4: Timer status register 4 (8 bits) Figure 8.5 Block Diagram of Channel 4 Rev.3.00 Mar. 26, 2007 Page 198 of 682 REJ09B0353-0300 TSR4 Section 8 16-Bit Integrated Timer Unit (ITU) 8.1.3 Input/Output Pins Table 8.2 summarizes the ITU pins. Table 8.2 Channel Common ITU Pins Name Clock input A Abbreviation TCLKA Input/ Output Input Function External clock A input pin (phase-A input pin in phase counting mode) External clock B input pin (phase-B input pin in phase counting mode) External clock C input pin External clock D input pin GRA0 output compare or input capture pin PWM output pin in PWM mode GRB0 output compare or input capture pin GRA1 output compare or input capture pin PWM output pin in PWM mode GRB1 output compare or input capture pin GRA2 output compare or input capture pin PWM output pin in PWM mode GRB2 output compare or input capture pin GRA3 output compare or input capture pin PWM output pin in PWM mode, complementary PWM mode, or resetsynchronized PWM mode GRB3 output compare or input capture pin PWM output pin in complementary PWM mode or reset-synchronized PWM mode Clock input B TCLKB Input Clock input C Clock input D 0 Input capture/output compare A0 Input capture/output compare B0 1 Input capture/output compare A1 Input capture/output compare B1 2 Input capture/output compare A2 Input capture/output compare B2 3 Input capture/output compare A3 TCLKC TCLKD TIOCA0 TIOCB0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 Input Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input capture/output compare B3 TIOCB3 Input/ output Rev.3.00 Mar. 26, 2007 Page 199 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Abbreviation TIOCA4 Input/ Output Input/ output Channel 4 Name Input capture/output compare A4 Function GRA4 output compare or input capture pin PWM output pin in PWM mode, complementary PWM mode, or resetsynchronized PWM mode GRB4 output compare or input capture pin PWM output pin in complementary PWM mode or reset-synchronized PWM mode PWM output pin in complementary PWM mode or reset-synchronized PWM mode PWM output pin in complementary PWM mode or reset-synchronized PWM mode Input capture/output compare B4 TIOCB4 Input/ output Output Output Output compare XA4 TOCXA4 Output compare XB4 TOCXB4 Rev.3.00 Mar. 26, 2007 Page 200 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.1.4 Register Configuration Table 8.3 summarizes the ITU registers. Table 8.3 Channel Common ITU Registers Address* H'FF60 H'FF61 H'FF62 H'FF63 H'FF90 H'FF91 1 Name Timer start register Timer synchro register Timer mode register Timer function control register Timer output master enable register Timer output control register Timer control register 0 Timer I/O control register 0 Timer interrupt enable register 0 Timer status register 0 Timer counter 0 (high) Timer counter 0 (low) General register A0 (high) General register A0 (low) General register B0 (high) General register B0 (low) Timer control register 1 Timer I/O control register 1 Timer interrupt enable register 1 Timer status register 1 Timer counter 1 (high) Timer counter 1 (low) General register A1 (high) General register A1 (low) General register B1 (high) General register B1 (low) Abbreviation TSTR TSNC TMDR TFCR TOER TOCR TCR0 TIOR0 TIER0 TSR0 TCNT0H TCNT0L GRA0H GRA0L GRB0H GRB0L TCR1 TIOR1 TIER1 TSR1 TCNT1H TCNT1L GRA1H GRA1L GRB1H GRB1L R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W 2 2 Initial Value H'E0 H'E0 H'80 H'C0 H'FF H'FF H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF 0 H'FF64 H'FF65 H'FF66 H'FF67 H'FF68 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D 1 H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF75 H'FF76 H'FF77 Rev.3.00 Mar. 26, 2007 Page 201 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Abbreviation TCR2 TIOR2 TIER2 TSR2 TCNT2H TCNT2L GRA2H GRA2L GRB2H GRB2L TCR3 TIOR3 TIER3 TSR3 TCNT3H TCNT3L GRA3H GRA3L GRB3H GRB3L BRA3H BRA3L BRB3H BRB3L Initial Value H'80 H'88 H'F8 2 Channel 2 Address* H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF7F H'FF80 H'FF81 1 Name Timer control register 2 Timer I/O control register 2 Timer interrupt enable register 2 Timer status register 2 Timer counter 2 (high) Timer counter 2 (low) General register A2 (high) General register A2 (low) General register B2 (high) General register B2 (low) Timer control register 3 Timer I/O control register 3 Timer interrupt enable register 3 Timer status register 3 Timer counter 3 (high) Timer counter 3 (low) General register A3 (high) General register A3 (low) General register B3 (high) General register B3 (low) Buffer register A3 (high) Buffer register A3 (low) Buffer register B3 (high) Buffer register B3 (low) R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'80 H'88 H'F8 H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'FF H'FF H'FF H'FF 3 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF87 H'FF88 H'FF89 H'FF8A H'FF8B H'FF8C H'FF8D H'FF8E H'FF8F Rev.3.00 Mar. 26, 2007 Page 202 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Abbreviation TCR4 TIOR4 TIER4 TSR4 TCNT4H TCNT4L GRA4H GRA4L GRB4H GRB4L BRA4H BRA4L BRB4H BRB4L Initial Value H'80 H'88 H'F8 2 Channel 4 Address* H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF9A H'FF9B H'FF9C H'FF9D H'FF9E H'FF9F 1 Name Timer control register 4 Timer I/O control register 4 Timer interrupt enable register 4 Timer status register 4 Timer counter 4 (high) Timer counter 4 (low) General register A4 (high) General register A4 (low) General register B4 (high) General register B4 (low) Buffer register A4 (high) Buffer register A4 (low) Buffer register B4 (high) Buffer register B4 (low) R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W H'F8 H'00 H'00 H'FF H'FF H'FF H'FF H'FF H'FF H'FF H'FF Notes: 1. The lower 16 bits of the address are indicated. 2. Only 0 can be written, to clear flags. Rev.3.00 Mar. 26, 2007 Page 203 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2 8.2.1 Register Descriptions Timer Start Register (TSTR) TSTR is an 8-bit readable/writable register that starts and stops the timer counter (TCNT) in channels 0 to 4. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- Reserved bits 5 -- 1 -- 4 STR4 0 R/W 3 STR3 0 R/W 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Counter start 4 to 0 These bits start and stop TCNT4 to TCNT0 TSTR is initialized to H'E0 by a reset and in standby mode. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bit 4--Counter Start 4 (STR4): Starts and stops timer counter 4 (TCNT4). Bit4 STR4 0 1 Description TCNT4 is halted TCNT4 is counting (Initial value) Bit 3--Counter Start 3 (STR3): Starts and stops timer counter 3 (TCNT3). Bit 3 STR3 0 1 Description TCNT3 is halted TCNT3 is counting (Initial value) Rev.3.00 Mar. 26, 2007 Page 204 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2--Counter Start 2 (STR2): Starts and stops timer counter 2 (TCNT2). Bit 2 STR2 0 1 Description TCNT2 is halted TCNT2 is counting (Initial value) Bit 1--Counter Start 1 (STR1): Starts and stops timer counter 1 (TCNT1). Bit 1 STR1 0 1 Description TCNT1 is halted TCNT1 is counting (Initial value) Bit 0--Counter Start 0 (STR0): Starts and stops timer counter 0 (TCNT0). Bit 0 STR0 0 1 Description TCNT0 is halted TCNT0 is counting (Initial value) Rev.3.00 Mar. 26, 2007 Page 205 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.2 Timer Synchro Register (TSNC) TSNC is an 8-bit readable/writable register that selects whether channels 0 to 4 operate independently or synchronously. Channels are synchronized by setting the corresponding bits to 1. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- Reserved bits 5 -- 1 -- 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Timer sync 4 to 0 These bits synchronize channels 4 to 0 TSNC is initialized to H'E0 by a reset and in standby mode. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bit 4--Timer Sync 4 (SYNC4): Selects whether channel 4 operates independently or synchronously. Bit 4 SYNC4 0 1 Description Channel 4's timer counter (TCNT4) operates independently TCNT4 is preset and cleared independently of other channels (Initial value) Channel 4 operates synchronously TCNT4 can be synchronously preset and cleared Bit 3--Timer Sync 3 (SYNC3): Selects whether channel 3 operates independently or synchronously. Bit 3 SYNC3 0 1 Description Channel 3's timer counter (TCNT3) operates independently TCNT3 is preset and cleared independently of other channels (Initial value) Channel 3 operates synchronously TCNT3 can be synchronously preset and cleared Rev.3.00 Mar. 26, 2007 Page 206 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2--Timer Sync 2 (SYNC2): Selects whether channel 2 operates independently or synchronously. Bit 2 SYNC2 0 1 Description Channel 2's timer counter (TCNT2) operates independently TCNT2 is preset and cleared independently of other channels (Initial value) Channel 2 operates synchronously TCNT2 can be synchronously preset and cleared Bit 1--Timer Sync 1 (SYNC1): Selects whether channel 1 operates independently or synchronously. Bit 1 SYNC1 0 1 Description Channel 1's timer counter (TCNT1) operates independently TCNT1 is preset and cleared independently of other channels (Initial value) Channel 1 operates synchronously TCNT1 can be synchronously preset and cleared Bit 0--Timer Sync 0 (SYNC0): Selects whether channel 0 operates independently or synchronously. Bit 0 SYNC0 0 1 Description Channel 0's timer counter (TCNT0) operates independently TCNT0 is preset and cleared independently of other channels (Initial value) Channel 0 operates synchronously TCNT0 can be synchronously preset and cleared Rev.3.00 Mar. 26, 2007 Page 207 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.3 Timer Mode Register (TMDR) TMDR is an 8-bit readable/writable register that selects PWM mode for channels 0 to 4. It also selects phase counting mode and the overflow flag (OVF) setting conditions for channel 2. Bit Initial value Read/Write 7 -- 1 -- 6 MDF 0 R/W 5 FDIR 0 R/W 4 PWM4 0 R/W 3 PWM3 0 R/W 2 PWM2 0 R/W 1 PWM1 0 R/W 0 PWM0 0 R/W PWM mode 4 to 0 These bits select PWM mode for channels 4 to 0 Flag direction Selects the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2) Phase counting mode flag Selects phase counting mode for channel 2 Reserved bit TMDR is initialized to H'80 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bit 6--Phase Counting Mode Flag (MDF): Selects whether channel 2 operates normally or in phase counting mode. Bit 6 MDF 0 1 Description Channel 2 operates normally Channel 2 operates in phase counting mode (Initial value) When MDF is set to 1 to select phase counting mode, timer counter 2 (TCNT2) operates as an up/down-counter and pins TCLKA and TCLKB become counter clock input pins. TCNT2 counts both rising and falling edges of TCLKA and TCLKB, and counts up or down as follows. Counting Direction TCLKA pin TCLKB pin Low Down-Counting High High Low High Up-Counting Low Low High Rev.3.00 Mar. 26, 2007 Page 208 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) In phase counting mode channel 2 operates as above regardless of the external clock edges selected by bits CKEG1 and CKEG0 and the clock source selected by bits TPSC2 to TPSC0 in timer control register 2 (TCR2). Phase counting mode takes precedence over these settings. The counter clearing condition selected by the CCLR1 and CCLR0 bits in TCR2 and the compare match/input capture settings and interrupt functions of timer I/O control register 2 (TIOR2), timer interrupt enable register 2 (TIER2), and timer status register 2 (TSR2) remain effective in phase counting mode. Bit 5--Flag Direction (FDIR): Designates the setting condition for the overflow flag (OVF) in timer status register 2 (TSR2). The FDIR designation is valid in all modes in channel 2. Bit 5 FDIR 0 1 Description OVF is set to 1 in TSR2 when TCNT2 overflows or underflows OVF is set to 1 in TSR2 when TCNT2 overflows (Initial value) Bit 4--PWM Mode 4 (PWM4): Selects whether channel 4 operates normally or in PWM mode. Bit 4 PWM4 0 1 Description Channel 4 operates normally Channel 4 operates in PWM mode (Initial value) When bit PWM4 is set to 1 to select PWM mode, pin TIOCA4 becomes a PWM output pin. The output goes to 1 at compare match with general register A4 (GRA4), and to 0 at compare match with general register B4 (GRB4). If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and CMD0 in the timer function control register (TFCR), the CMD1 and CMD0 setting takes precedence and the PWM4 setting is ignored. Bit 3--PWM Mode 3 (PWM3): Selects whether channel 3 operates normally or in PWM mode. Bit 3 PWM3 0 1 Description Channel 3 operates normally Channel 3 operates in PWM mode (Initial value) Rev.3.00 Mar. 26, 2007 Page 209 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) When bit PWM3 is set to 1 to select PWM mode, pin TIOCA3 becomes a PWM output pin. The output goes to 1 at compare match with general register A3 (GRA3), and to 0 at compare match with general register B3 (GRB3). If complementary PWM mode or reset-synchronized PWM mode is selected by bits CMD1 and CMD0 in the timer function control register (TFCR), the CMD1 and CMD0 setting takes precedence and the PWM3 setting is ignored. Bit 2--PWM Mode 2 (PWM2): Selects whether channel 2 operates normally or in PWM mode. Bit 2 PWM2 0 1 Description Channel 2 operates normally Channel 2 operates in PWM mode (Initial value) When bit PWM2 is set to 1 to select PWM mode, pin TIOCA2 becomes a PWM output pin. The output goes to 1 at compare match with general register A2 (GRA2), and to 0 at compare match with general register B2 (GRB2). Bit 1--PWM Mode 1 (PWM1): Selects whether channel 1 operates normally or in PWM mode. Bit 1 PWM1 0 1 Description Channel 1 operates normally Channel 1 operates in PWM mode (Initial value) When bit PWM1 is set to 1 to select PWM mode, pin TIOCA1 becomes a PWM output pin. The output goes to 1 at compare match with general register A1 (GRA1), and to 0 at compare match with general register B1 (GRB1). Bit 0--PWM Mode 0 (PWM0): Selects whether channel 0 operates normally or in PWM mode. Bit 0 PWM0 0 1 Description Channel 0 operates normally Channel 0 operates in PWM mode (Initial value) When bit PWM0 is set to 1 to select PWM mode, pin TIOCA0 becomes a PWM output pin. The output goes to 1 at compare match with general register A0 (GRA0), and to 0 at compare match with general register B0 (GRB0). Rev.3.00 Mar. 26, 2007 Page 210 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.4 Timer Function Control Register (TFCR) TFCR is an 8-bit readable/writable register that selects complementary PWM mode, resetsynchronized PWM mode, and buffering for channels 3 and 4. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 CMD1 0 R/W 4 CMD0 0 R/W 3 BFB4 0 R/W 2 BFA4 0 R/W 1 BFB3 0 R/W 0 BFA3 0 R/W Reserved bits Combination mode 1/0 These bits select complementary PWM mode or reset-synchronized PWM mode for channels 3 and 4 Buffer mode B4 and A4 These bits select buffering of general registers (GRB4 and GRA4) by buffer registers (BRB4 and BRA4) in channel 4 Buffer mode B3 and A3 These bits select buffering of general registers (GRB3 and GRA3) by buffer registers (BRB3 and BRA3) in channel 3 TFCR is initialized to H'C0 by a reset and in standby mode. Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 211 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bits 5 and 4--Combination Mode 1 and 0 (CMD1, CMD0): These bits select whether channels 3 and 4 operate in normal mode, complementary PWM mode, or reset-synchronized PWM mode. Bit 5 CMD1 0 Bit 4 CMD0 0 1 1 0 1 Channels 3 and 4 operate together in complementary PWM mode Channels 3 and 4 operate together in reset-synchronized PWM mode Description Channels 3 and 4 operate normally (Initial value) Before selecting reset-synchronized PWM mode or complementary PWM mode, halt the timer counter or counters that will be used in these modes. When these bits select complementary PWM mode or reset-synchronized PWM mode, they take precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of timer sync bits SYNC4 and SYNC3 in the timer synchro register (TSNC) are valid in complementary PWM mode and reset-synchronized PWM mode, however. When complementary PWM mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and SYNC4 both to 1 in TSNC). Bit 3--Buffer Mode B4 (BFB4): Selects whether GRB4 operates normally in channel 4, or whether GRB4 is buffered by BRB4. Bit 3 BFB4 0 1 Description GRB4 operates normally GRB4 is buffered by BRB4 (Initial value) Bit 2--Buffer Mode A4 (BFA4): Selects whether GRA4 operates normally in channel 4, or whether GRA4 is buffered by BRA4. Bit 2 BFA4 0 1 Description GRA4 operates normally GRA4 is buffered by BRA4 (Initial value) Rev.3.00 Mar. 26, 2007 Page 212 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 1--Buffer Mode B3 (BFB3): Selects whether GRB3 operates normally in channel 3, or whether GRB3 is buffered by BRB3. Bit 1 BFB3 0 1 Description GRB3 operates normally GRB3 is buffered by BRB3 (Initial value) Bit 0--Buffer Mode A3 (BFA3): Selects whether GRA3 operates normally in channel 3, or whether GRA3 is buffered by BRA3. Bit 0 BFA3 0 1 Description GRA3 operates normally GRA3 is buffered by BRA3 (Initial value) Rev.3.00 Mar. 26, 2007 Page 213 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.5 Timer Output Master Enable Register (TOER) TOER is an 8-bit readable/writable register that enables or disables output settings for channels 3 and 4. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 EXB4 1 R/W 4 EXA4 1 R/W 3 EB3 1 R/W 2 EB4 1 R/W 1 EA4 1 R/W 0 EA3 1 R/W Reserved bits Master enable TOCXA4, TOCXB4 These bits enable or disable output settings for pins TOCXA4 and TOCXB4 Master enable TIOCA3, TIOCB3 , TIOCA4, TIOCB4 These bits enable or disable output settings for pins TIOCA3, TIOCB3 , TIOCA4, and TIOCB4 TOER is initialized to H'FF by a reset and in standby mode. Bits 7 and 6--Reserved: These bits cannot be modified and are always read as 1. Bit 5--Master Enable TOCXB4 (EXB4): Enables or disables ITU output at pin TOCXB4. Bit 5 EXB4 0 Description TOCXB4 output is disabled regardless of TFCR settings (TOCXB4 operates as a generic input/output pin). If XTGD = 0, EXB4 is cleared to 0 when input capture A occurs in channel 1. TOCXB4 is enabled for output according to TFCR settings (Initial value) 1 Bit 4--Master Enable TOCXA4 (EXA4): Enables or disables ITU output at pin TOCXA4. Bit 4 EXA4 0 Description TOCXA4 output is disabled regardless of TFCR settings (TOCXA4 operates as a generic input/output pin). If XTGD = 0, EXA4 is cleared to 0 when input capture A occurs in channel 1. 1 TOCXA4 is enabled for output according to TFCR settings (Initial value) Rev.3.00 Mar. 26, 2007 Page 214 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 3--Master Enable TIOCB3 (EB3): Enables or disables ITU output at pin TIOCB3. Bit 3 EB3 0 Description TIOCB3 output is disabled regardless of TIOR3 and TFCR settings (TIOCB3 operates as a generic input/output pin). If XTGD = 0, EB3 is cleared to 0 when input capture A occurs in channel 1. 1 TIOCB3 is enabled for output according to TIOR3 and TFCR settings (Initial value) Bit 2--Master Enable TIOCB4 (EB4): Enables or disables ITU output at pin TIOCB4. Bit 2 EB4 0 Description TIOCB4 output is disabled regardless of TIOR4 and TFCR settings (TIOCB4 operates as a generic input/output pin). If XTGD = 0, EB4 is cleared to 0 when input capture A occurs in channel 1. 1 TIOCB4 is enabled for output according to TIOR4 and TFCR settings (Initial value) Bit 1--Master Enable TIOCA4 (EA4): Enables or disables ITU output at pin TIOCA4. Bit 1 EA4 0 Description TIOCA4 output is disabled regardless of TIOR4, TMDR, and TFCR settings (TIOCA4 operates as a generic input/output pin). If XTGD = 0, EA4 is cleared to 0 when input capture A occurs in channel 1. 1 TIOCA4 is enabled for output according to TIOR4, TMDR, and TFCR settings (Initial value) Bit 0--Master Enable TIOCA3 (EA3): Enables or disables ITU output at pin TIOCA3. Bit 0 EA3 0 Description TIOCA3 output is disabled regardless of TIOR3, TMDR, and TFCR settings (TIOCA3 operates as a generic input/output pin). If XTGD = 0, EA3 is cleared to 0 when input capture A occurs in channel 1. 1 TIOCA3 is enabled for output according to TIOR3, TMDR, and TFCR settings (Initial value) Rev.3.00 Mar. 26, 2007 Page 215 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.6 Timer Output Control Register (TOCR) TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- Reserved bits 5 -- 1 -- 4 XTGD 1 R/W 3 -- 1 -- 2 -- 1 -- 1 OLS4 1 R/W 0 OLS3 1 R/W Output level select 3, 4 These bits select output levels in complementary PWM mode and resetsynchronized PWM mode Reserved bits External trigger disable Selects externally triggered disabling of output in complementary PWM mode and reset-synchronized PWM mode The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode and reset-synchronized PWM mode. These settings do not affect other modes. TOCR is initialized to H'FF by a reset and in standby mode. Bits 7 to 5--Reserved: These bits cannot be modified and are always read as 1. Bit 4--External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output in complementary PWM mode and reset-synchronized PWM mode. Bit 4 XTGD 0 Description Input capture A in channel 1 is used as an external trigger signal in complementary PWM mode and reset-synchronized PWM mode. When an external trigger occurs, bits 5 to 0 in the timer output master enable register (TOER) are cleared to 0, disabling ITU output. 1 External triggering is disabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 216 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bits 3 and 2--Reserved: These bits cannot be modified and are always read as 1. Bit 1--Output Level Select 4 (OLS4): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 1 OLS4 0 1 Description TIOCA3, TIOCA4, and TIOCB4 pin outputs are inverted TIOCA3, TIOCA4, and TIOCB4 pin outputs are not inverted (Initial value) Bit 0--Output Level Select 3 (OLS3): Selects output levels in complementary PWM mode and reset-synchronized PWM mode. Bit 0 OLS3 0 1 Description TIOCB3, TOCXA4, and TOCXB4 pin outputs are inverted TIOCB3, TOCXA4, and TOCXB4 pin outputs are not inverted (Initial value) Rev.3.00 Mar. 26, 2007 Page 217 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.7 Timer Counters (TCNT) TCNT is a 16-bit counter. The ITU has five TCNTs, one for each channel. Channel 0 1 2 3 4 Abbreviation TCNT0 TCNT1 TCNT2 TCNT3 TCNT4 Phase counting mode: up/down-counter Other modes: up-counter Complementary PWM mode: up/down-counter Other modes: up-counter Function Up-counter Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Each TCNT is a 16-bit readable/writable register that counts pulse inputs from a clock source. The clock source is selected by bits TPSC2 to TPSC0 in the timer control register (TCR). TCNT0 and TCNT1 are up-counters. TCNT2 is an up/down-counter in phase counting mode and an up-counter in other modes. TCNT3 and TCNT4 are up/down-counters in complementary PWM mode and up-counters in other modes. TCNT can be cleared to H'0000 by compare match with general register A or B (GRA or GRB) or by input capture to GRA or GRB (counter clearing function) in the same channel. When TCNT overflows (changes from H'FFFF to H'0000), the overflow flag (OVF) is set to 1 in the timer status register (TSR) of the corresponding channel. When TCNT underflows (changes from H'0000 to H'FFFF), the overflow flag (OVF) is set to 1 in TSR of the corresponding channel. The TCNTs are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. Each TCNT is initialized to H'0000 by a reset and in standby mode. Rev.3.00 Mar. 26, 2007 Page 218 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.8 General Registers (GRA, GRB) The general registers are 16-bit registers. The ITU has 10 general registers, two in each channel. Channel 0 1 2 3 4 Abbreviation GRA0, GRB0 GRA1, GRB1 GRA2, GRB2 GRA3, GRB3 GRA4, GRB4 Output compare/input capture register; can be by buffer registers BRA and BRB Function Output compare/input capture register Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A general register is a 16-bit readable/writable register that can function as either an output compare register or an input capture register. The function is selected by settings in the timer I/O control register (TIOR). When a general register is used as an output compare register, its value is constantly compared with the TCNT value. When the two values match (compare match), the IMFA or IMFB flag is set to 1 in the timer status register (TSR). Compare match output can be selected in TIOR. When a general register is used as an input capture register, rising edges, falling edges, or both edges of an external input capture signal are detected and the current TCNT value is stored in the general register. The corresponding IMFA or IMFB flag in TSR is set to 1 at the same time. The valid edge or edges of the input capture signal are selected in TIOR. TIOR settings are ignored in PWM mode, complementary PWM mode, and reset-synchronized PWM mode. General registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word access or byte access. General registers are initialized to the output compare function (with no output signal) by a reset and in standby mode. The initial value is H'FFFF. Rev.3.00 Mar. 26, 2007 Page 219 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.9 Buffer Registers (BRA, BRB) The buffer registers are 16-bit registers. The ITU has four buffer registers, two each in channels 3 and 4. Channel 3 4 Abbreviation BRA3, BRB3 BRA4, BRB4 Function Used for buffering * When the corresponding GRA or GRB functions as an output compare register, BRA or BRB can function as an output compare buffer register: the BRA or BRB value is automatically transferred to GRA or GRB at compare match When the corresponding GRA or GRB functions as an input capture register, BRA or BRB can function as an input capture buffer register: the GRA or GRB value is automatically transferred to BRA or BRB at input capture * Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W A buffer register is a 16-bit readable/writable register that is used when buffering is selected. Buffering can be selected independently by bits BFB4, BFA4, BFB3, and BFA3 in TFCR. The buffer register and general register operate as a pair. When the general register functions as an output compare register, the buffer register functions as an output compare buffer register. When the general register functions as an input capture register, the buffer register functions as an input capture buffer register. The buffer registers are linked to the CPU by an internal 16-bit bus and can be written or read by either word or byte access. Buffer registers are initialized to H'FFFF by a reset and in standby mode. Rev.3.00 Mar. 26, 2007 Page 220 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.10 Timer Control Registers (TCR) TCR is an 8-bit register. The ITU has five TCRs, one in each channel. Channel 0 1 2 3 4 Abbreviation TCR0 TCR1 TCR2 TCR3 TCR4 Function TCR controls the timer counter. The TCRs in all channels are functionally identical. When phase counting mode is selected in channel 2, the settings of bits CKEG1 and CKEG0 and TPSC2 to TPSC0 in TCR2 are ignored. Bit Initial value Read/Write 7 -- 1 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Timer prescaler 2 to 0 These bits select the counter clock Clock edge 1/0 These bits select external clock edges Counter clear 1/0 These bits select the counter clear source Reserved bit Each TCR is an 8-bit readable/writable register that selects the timer counter clock source, selects the edge or edges of external clock sources, and selects how the counter is cleared. TCR is initialized to H'80 by a reset and in standby mode. Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bits 6 and 5--Counter Clear 1/0 (CCLR1, CCLR0): These bits select how TCNT is cleared. Rev.3.00 Mar. 26, 2007 Page 221 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT is not cleared TCNT is cleared by GRA compare match or input capture* TCNT is cleared by GRB compare match or input capture* 1 1 (Initial value) Synchronous clear: TCNT is cleared in synchronization with other 2 synchronized timers* Notes: 1. TCNT is cleared by compare match when the general register functions as an output compare match register, and by input capture when the general register functions as an input capture register. 2. Selected in the timer synchro register (TSNC). Bits 4 and 3--Clock Edge 1/0 (CKEG1, CKEG0): These bits select external clock input edges when an external clock source is used. Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 -- Description Count rising edges Count falling edges Count both edges (Initial value) When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in TCR2 are ignored. Phase counting takes precedence. Bits 2 to 0--Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock source. Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Function Internal clock: Internal clock: /2 Internal clock: /4 Internal clock: /8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input External clock D: TCLKD input (Initial value) Rev.3.00 Mar. 26, 2007 Page 222 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) When bit TPSC2 is cleared to 0 an internal clock source is selected, and the timer counts only falling edges. When bit TPSC2 is set to 1 an external clock source is selected, and the timer counts the edge or edges selected by bits CKEG1 and CKEG0. When channel 2 is set to phase counting mode (MDF = 1 in TMDR), the settings of bits TPSC2 to TPSC0 in TCR2 are ignored. Phase counting takes precedence. 8.2.11 Timer I/O Control Register (TIOR) TIOR is an 8-bit register. The ITU has five TIORs, one in each channel. Channel 0 1 2 3 4 Abbreviation TIOR0 TIOR1 TIOR2 TIOR3 TIOR4 Function TIOR controls the general registers. Some functions differ in PWM mode. TIOR3 and TIOR4 settings are ignored when complementary PWM mode or reset-synchronized PWM mode is selected in channels 3 and 4. Bit Initial value Read/Write 7 -- 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W I/O control A2 to A0 These bits select GRA functions Reserved bit I/O control B2 to B0 These bits select GRB functions Reserved bit Each TIOR is an 8-bit readable/writable register that selects the output compare or input capture function for GRA and GRB, and specifies the functions of the TIOCA and TIOCB pins. If the output compare function is selected, TIOR also selects the type of output. If input capture is selected, TIOR also selects the edge or edges of the input capture signal. TIOR is initialized to H'88 by a reset and in standby mode. Rev.3.00 Mar. 26, 2007 Page 223 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 7--Reserved: This bit cannot be modified and is always read as 1. Bits 6 to 4--I/O Control B2 to B0 (IOB2 to IOB0): These bits select the GRB function. Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. After a reset, the output is 0 until the first compare match. 2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output instead. GRB is an input capture register Function GRB is an output compare register No output at compare match 0 output at GRB compare match* 1 output at GRB compare match* (Initial value) 1 1 Output toggles at GRB compare match 12 (1 output in channel 2)* * GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input Bit 3--Reserved: This bit cannot be modified and is always read as 1. Bits 2 to 0--I/O Control A2 to A0 (IOA2 to IOA0): These bits select the GRA function. Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 1 1 0 1 1 0 0 1 1 0 1 Notes: 1. After a reset, the output is 0 until the first compare match. 2. Channel 2 output cannot be toggled by compare match. This setting selects 1 output instead. GRA is an input capture register Function GRA is an output compare register No output at compare match 0 output at GRA compare match* 1 output at GRA compare match* (Initial value) 1 1 Output toggles at GRA compare match 12 (1 output in channel 2)* * GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input Rev.3.00 Mar. 26, 2007 Page 224 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.12 Timer Status Register (TSR) TSR is an 8-bit register. The ITU has five TSRs, one in each channel. Channel 0 1 2 3 4 Abbreviation TSR0 TSR1 TSR2 TSR3 TSR4 Function Indicates input capture, compare match, and overflow status Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- Reserved bits 4 -- 1 -- 3 -- 1 -- 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* 0 IMFA 0 R/(W)* Overflow flag Status flag indicating overflow or underflow Input capture/compare match flag B Status flag indicating GRB compare match or input capture Input capture/compare match flag A Status flag indicating GRA compare match or input capture Note: * Only 0 can be written to clear the flag. Each TSR is an 8-bit readable/writable register containing flags that indicate TCNT overflow or underflow and GRA or GRB compare match or input capture. These flags are interrupt sources and generate CPU interrupts if enabled by corresponding bits in the timer interrupt enable register (TIER). TSR is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 225 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2--Overflow Flag (OVF): This status flag indicates TCNT overflow or underflow. Bit 2 OVF 0 1 Notes: * Description [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF [Setting condition] TCNT overflowed from H'FFFF to H'0000, or underflowed from H'0000 to H'FFFF* TCNT underflow occurs when TCNT operates as an up/down-counter. Underflow occurs only under the following conditions: 1. Channel 2 operates in phase counting mode (MDF = 1 in TMDR) 2. Channels 3 and 4 operate in complementary PWM mode (CMD1 = 1 and CMD0 = 0 in TFCR) (Initial value) Bit 1--Input Capture/Compare Match Flag B (IMFB): This status flag indicates GRB compare match or input capture events. Bit 1 IMFB 0 1 Description [Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB [Setting conditions] * * TCNT = GRB when GRB functions as a compare match register. TCNT value is transferred to GRB by an input capture signal, when GRB functions as an input capture register. (Initial value) Bit 0--Input Capture/Compare Match Flag A (IMFA): This status flag indicates GRA compare match or input capture events. Bit 0 IMFA 0 1 Description [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA. [Setting conditions] * * TCNT = GRA when GRA functions as a compare match register. TCNT value is transferred to GRA by an input capture signal, when GRA functions as an input capture register. (Initial value) Rev.3.00 Mar. 26, 2007 Page 226 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.2.13 Timer Interrupt Enable Register (TIER) TIER is an 8-bit register. The ITU has five TIERs, one in each channel. Channel 0 1 2 3 4 Abbreviation TIER0 TIER1 TIER2 TIER3 TIER4 Function Enables or disables interrupt requests. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- Reserved bits 4 -- 1 -- 3 -- 1 -- 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 IMIEA 0 R/W Overflow interrupt enable Enables or disables OVF interrupts Input capture/compare match interrupt enable B Enables or disables IMFB interrupts Input capture/compare match interrupt enable A Enables or disables IMFA interrupts Each TIER is an 8-bit readable/writable register that enables and disables overflow interrupt requests and general register compare match and input capture interrupt requests. TIER is initialized to H'F8 by a reset and in standby mode. Bits 7 to 3--Reserved: These bits cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 227 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Bit 2--Overflow Interrupt Enable (OVIE): Enables or disables the interrupt requested by the overflow flag (OVF) in TSR when OVF is set to 1. Bit 2 OVIE 0 1 Description OVI interrupt requested by OVF is disabled OVI interrupt requested by OVF is enabled (Initial value) Bit 1--Input Capture/Compare Match Interrupt Enable B (IMIEB): Enables or disables the interrupt requested by the IMFB flag in TSR when IMFB is set to 1. Bit 1 IMIEB 0 1 Description IMIB interrupt requested by IMFB is disabled IMIB interrupt requested by IMFB is enabled (Initial value) Bit 0--Input Capture/Compare Match Interrupt Enable A (IMIEA): Enables or disables the interrupt requested by the IMFA flag in TSR when IMFA is set to 1. Bit 0 IMIEA 0 1 Description IMIA interrupt requested by IMFA is disabled IMIA interrupt requested by IMFA is enabled (Initial value) 8.3 8.3.1 CPU Interface 16-Bit Accessible Registers The timer counters (TCNTs), general registers A and B (GRAs and GRBs), and buffer registers A and B (BRAs and BRBs) are 16-bit registers, and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a word at a time, or a byte at a time. Figures 8.6 and 8.7 show examples of word access to a timer counter (TCNT). Figures 8.8, 8.9, 8.10, and 8.11 show examples of byte access to TCNTH and TCNTL. Rev.3.00 Mar. 26, 2007 Page 228 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Internal data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 8.6 Access to Timer Counter (CPU Writes to TCNT, Word) Internal data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 8.7 Access to Timer Counter (CPU Reads TCNT, Word) Internal data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 8.8 Access to Timer Counter (CPU Writes to TCNT, Upper Byte) Rev.3.00 Mar. 26, 2007 Page 229 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Internal data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 8.9 Access to Timer Counter (CPU Writes to TCNT, Lower Byte) Internal data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 8.10 Access to Timer Counter (CPU Reads TCNT, Upper Byte) Internal data bus H CPU L Bus interface H L Module data bus TCNTH TCNTL Figure 8.11 Access to Timer Counter (CPU Reads TCNT, Lower Byte) Rev.3.00 Mar. 26, 2007 Page 230 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.3.2 8-Bit Accessible Registers The registers other than the timer counters, general registers, and buffer registers are 8-bit registers. These registers are linked to the CPU by an internal 8-bit data bus. Figures 8.12 and 8.13 show examples of byte read and write access to a TCR. If a word-size data transfer instruction is executed, two byte transfers are performed. Internal data bus H CPU L Bus interface H L Module data bus TCR Figure 8.12 TCR Access (CPU Writes to TCR) Internal data bus H CPU L Bus interface H L Module data bus TCR Figure 8.13 TCR Access (CPU Reads TCR) Rev.3.00 Mar. 26, 2007 Page 231 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4 8.4.1 Operation Overview A summary of operations in the various modes is given below. Normal Operation: Each channel has a timer counter and general registers. The timer counter counts up, and can operate as a free-running counter, periodic counter, or external event counter. General registers A and B can be used for input capture or output compare. Synchronous Operation: The timer counters in designated channels are preset synchronously. Data written to the timer counter in any one of these channels is simultaneously written to the timer counters in the other channels as well. The timer counters can also be cleared synchronously if so designated by the CCLR1 and CCLR0 bits in the TCRs. PWM Mode: A PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match A and to 0 at compare match B. The duty cycle can be varied from 0% to 100% depending on the settings of GRA and GRB. When a channel is set to PWM mode, its GRA and GRB automatically become output compare registers. Reset-Synchronized PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with complementary waveforms. (The three phases are related by having a common transition point.) When reset-synchronized PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins, and TCNT3 operates as an up-counter. TCNT4 operates independently, and is not compared with GRA4 or GRB4. Complementary PWM Mode: Channels 3 and 4 are paired for three-phase PWM output with non-overlapping complementary waveforms. When complementary PWM mode is selected GRA3, GRB3, GRA4, and GRB4 automatically function as output compare registers, and TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 function as PWM output pins. TCNT3 and TCNT4 operate as up/down-counters. Phase Counting Mode: The phase relationship between two clock signals input at TCLKA and TCLKB is detected and TCNT2 counts up or down accordingly. When phase counting mode is selected TCLKA and TCLKB become clock input pins and TCNT2 operates as an up/downcounter. Rev.3.00 Mar. 26, 2007 Page 232 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Buffering: * If the general register is an output compare register When compare match occurs the buffer register value is transferred to the general register. * If the general register is an input capture register When input capture occurs the TCNT value is transferred to the general register, and the previous general register value is transferred to the buffer register. * Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. * Reset-synchronized PWM mode The buffer register value is transferred to the general register at GRA3 compare match. Rev.3.00 Mar. 26, 2007 Page 233 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.2 Basic Functions Counter Operation When one of bits STR0 to STR4 is set to 1 in the timer start register (TSTR), the timer counter (TCNT) in the corresponding channel starts counting. The counting can be free-running or periodic. Sample setup procedure for counter: Figure 8.14 shows a sample procedure for setting up a counter. Counter setup Select counter clock 1 Type of counting? Yes Periodic counting No Free-running counting Select counter clear source 2 Select output compare register function 3 Set period 4 Start counter Periodic counter 5 Start counter Free-running counter 5 Figure 8.14 Counter Setup Procedure (Example) Rev.3.00 Mar. 26, 2007 Page 234 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal. 2. For periodic counting, set CCLR1 and CCLR0 in TCR to have TCNT cleared at GRA compare match or GRB compare match. 3. Set TIOR to select the output compare function of GRA or GRB, whichever was selected in step 2. 4. Write the count period in GRA or GRB, whichever was selected in step 2. 5. Set the STR bit to 1 in TSTR to start the timer counter. Free-running and periodic counter operation: A reset leaves the counters (TCNTs) in ITU channels 0 to 4 all set as free-running counters. A free-running counter starts counting up when the corresponding bit in TSTR is set to 1. When the count overflows from H'FFFF to H'0000, the overflow flag (OVF) is set to 1 in the timer status register (TSR). If the corresponding OVIE bit is set to 1 in the timer interrupt enable register, a CPU interrupt is requested. After the overflow, the counter continues counting up from H'0000. Figure 8.15 illustrates free-running counting. TCNT value H'FFFF H'0000 STR0 to STR4 bit OVF Time Figure 8.15 Free-Running Counter Operation When a channel is set to have its counter cleared by compare match, in that channel TCNT operates as a periodic counter. Select the output compare function of GRA or GRB, set bit CCLR1 or CCLR0 in the timer control register (TCR) to have the counter cleared by compare match, and set the count period in GRA or GRB. After these settings, the counter starts counting up as a periodic counter when the corresponding bit is set to 1 in TSTR. When the count matches GRA or GRB, the IMFA or IMFB flag is set to 1 in TSR and the counter is cleared to H'0000. If the corresponding IMIEA or IMIEB bit is set to 1 in TIER, a CPU interrupt is requested at this time. After the compare match, TCNT continues counting up from H'0000. Figure 8.16 illustrates periodic counting. Rev.3.00 Mar. 26, 2007 Page 235 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) TCNT value GR Counter cleared by general register compare match H'0000 STR bit IMF Time Figure 8.16 Periodic Counter Operation Count timing: * Internal clock source Bits TPSC2 to TPSC0 in TCR select the system clock () or one of three internal clock sources obtained by prescaling the system clock (/2, /4, /8). Figure 8.17 shows the timing. Internal clock TCNT input TCNT N-1 N N+1 Figure 8.17 Count Timing for Internal Clock Sources * External clock source Bits TPSC2 to TPSC0 in TCR select an external clock input pin (TCLKA to TCLKD), and its valid edge or edges are selected by bits CKEG1 and CKEG0. The rising edge, falling edge, or both edges can be selected. The pulse width of the external clock signal must be at least 1.5 system clocks when a single edge is selected, and at least 2.5 system clocks when both edges are selected. Shorter pulses will not be counted correctly. Figure 8.18 shows the timing when both edges are detected. Rev.3.00 Mar. 26, 2007 Page 236 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) External clock input TCNT input TCNT N-1 N N+1 Figure 8.18 Count Timing for External Clock Sources (when Both Edges are Detected) Waveform Output by Compare Match In ITU channels 0, 1, 3, and 4, compare match A or B can cause the output at the TIOCA or TIOCB pin to go to 0, go to 1, or toggle. In channel 2 the output can only go to 0 or go to 1. Sample setup procedure for waveform output by compare match: Figure 8.19 shows a sample procedure for setting up waveform output by compare match. Output setup Select waveform output mode 1 1. Select the compare match output mode (0, 1, or toggle) in TIOR. When a waveform output mode is selected, the pin switches from its generic input/ output function to the output compare function (TIOCA or TIOCB). An output compare pin outputs 0 until the first compare match occurs. Set output timing 2 2. Set a value in GRA or GRB to designate the compare match timing. Start counter 3 3. Set the STR bit to 1 in TSTR to start the timer counter. Waveform output Figure 8.19 Setup Procedure for Waveform Output by Compare Match (Example) Rev.3.00 Mar. 26, 2007 Page 237 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of waveform output: Figure 8.20 shows examples of 0 and 1 output. TCNT operates as a free-running counter, 0 output is selected for compare match A, and 1 output is selected for compare match B. When the pin is already at the selected output level, the pin level does not change. TCNT value H'FFFF GRB GRA H'0000 TIOCB Time No change No change 1 output TIOCA No change No change 0 output Figure 8.20 0 and 1 Output (Examples) Figure 8.21 shows examples of toggle output. TCNT operates as a periodic counter, cleared by compare match B. Toggle output is selected for both compare match A and B. TCNT value GRB Counter cleared by compare match with GRB GRA H'0000 TIOCB Time Toggle output Toggle output TIOCA Figure 8.21 Toggle Output (Example) Rev.3.00 Mar. 26, 2007 Page 238 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Output compare timing: The compare match signal is generated in the last state in which TCNT and the general register match (when TCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TIOR is output at the output compare pin (TIOCA or TIOCB). When TCNT matches a general register, the compare match signal is not generated until the next counter clock pulse. Figure 8.22 shows the output compare timing. TCNT input clock TCNT N N+1 GR Compare match signal TIOCA, TIOCB N Figure 8.22 Output Compare Timing Rev.3.00 Mar. 26, 2007 Page 239 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Input Capture Function The TCNT value can be captured into a general register when a transition occurs at an input capture/output compare pin (TIOCA or TIOCB). Capture can take place on the rising edge, falling edge, or both edges. The input capture function can be used to measure pulse width or period. Sample setup procedure for input capture: Figure 8.23 shows a sample procedure for setting up input capture. Input selection Select input-capture input 1 1. Set TIOR to select the input capture function of a general register and the rising edge, falling edge, or both edges of the input capture signal. Clear the port data direction bit to 0 before making these TIOR settings. Start counter 2 2. Set the STR bit to 1 in TSTR to start the timer counter. Input capture Figure 8.23 Setup Procedure for Input Capture (Example) Rev.3.00 Mar. 26, 2007 Page 240 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of input capture: Figure 8.24 illustrates input capture when the falling edge of TIOCB and both edges of TIOCA are selected as capture edges. TCNT is cleared by input capture into GRB. TCNT value H'0180 H'0160 H'0005 H'0000 TIOCB Counter cleared by TIOCB input (falling edge) Time TIOCA GRA H'0005 H'0160 GRB H'0180 Figure 8.24 Input Capture (Example) Rev.3.00 Mar. 26, 2007 Page 241 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Input capture signal timing: Input capture on the rising edge, falling edge, or both edges can be selected by settings in TIOR. Figure 8.25 shows the timing when the rising edge is selected. The pulse width of the input capture signal must be at least 1.5 system clocks for single-edge capture, and 2.5 system clocks for capture of both edges. Input-capture input Internal input capture signal TCNT N GRA, GRB N Figure 8.25 Input Capture Signal Timing Rev.3.00 Mar. 26, 2007 Page 242 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.3 Synchronization The synchronization function enables two or more timer counters to be synchronized by writing the same data to them simultaneously (synchronous preset). With appropriate TCR settings, two or more timer counters can also be cleared simultaneously (synchronous clear). Synchronization enables additional general registers to be associated with a single time base. Synchronization can be selected for all channels (0 to 4). Sample Setup Procedure for Synchronization Figure 8.26 shows a sample procedure for setting up synchronization. Setup for synchronization Select synchronization 1 Synchronous preset Synchronous clear Write to TCNT 2 Clearing synchronized to this channel? Yes Select counter clear source No 3 Select counter clear source 4 Start counter 5 Start counter 5 Synchronous preset Counter clear Synchronous clear 1. Set the SYNC bits to 1 in TSNC for the channels to be synchronized. 2. When a value is written in TCNT in one of the synchronized channels, the same value is simultaneously written in TCNT in the other channels. 3. Set the CCLR1 or CCLR0 bit in TCR to have the counter cleared by compare match or input capture. 4. Set the CCLR1 and CCLR0 bits in TCR to have the counter cleared synchronously. 5. Set the STR bits in TSTR to 1 to start the synchronized counters. Figure 8.26 Setup Procedure for Synchronization (Example) Rev.3.00 Mar. 26, 2007 Page 243 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Example of Synchronization Figure 8.27 shows an example of synchronization. Channels 0, 1, and 2 are synchronized, and are set to operate in PWM mode. Channel 0 is set for counter clearing by compare match with GRB0. Channels 1 and 2 are set for synchronous counter clearing. The timer counters in channels 0, 1, and 2 are synchronously preset, and are synchronously cleared by compare match with GRB0. A three-phase PWM waveform is output from pins TIOCA0, TIOCA1, and TIOCA2. For further information on PWM mode, see section 8.4.4, PWM Mode. Value of TCNT0 to TCNT2 Cleared by compare match with GRB0 GRB0 GRB1 GRA0 GRB2 GRA1 GRA2 H'0000 TIOCA0 Time TIOCA1 TIOCA2 Figure 8.27 Synchronization (Example) Rev.3.00 Mar. 26, 2007 Page 244 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.4 PWM Mode In PWM mode GRA and GRB are paired and a PWM waveform is output from the TIOCA pin. GRA specifies the time at which the PWM output changes to 1. GRB specifies the time at which the PWM output changes to 0. If either GRA or GRB is selected as the counter clear source, a PWM waveform with a duty cycle from 0% to 100% is output at the TIOCA pin. PWM mode can be selected in all channels (0 to 4). Table 8.4 summarizes the PWM output pins and corresponding registers. If the same value is set in GRA and GRB, the output does not change when compare match occurs. Table 8.4 Channel 0 1 2 3 4 PWM Output Pins and Registers Output Pin TIOCA0 TIOCA1 TIOCA2 TIOCA3 TIOCA4 1 Output GRA0 GRA1 GRA2 GRA3 GRA4 0 Output GRB0 GRB1 GRB2 GRB3 GRB4 Rev.3.00 Mar. 26, 2007 Page 245 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Sample Setup Procedure for PWM Mode Figure 8.28 shows a sample procedure for setting up PWM mode. PWM mode Select counter clock 1 Select counter clear source 2 Set GRA 3 Set GRB 4 Select PWM mode 5 Start counter 6 PWM mode 1. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source. If an external clock source is selected, set bits CKEG1 and CKEG0 in TCR to select the desired edge(s) of the external clock signal. 2. Set bits CCLR1 and CCLR0 in TCR to select the counter clear source. 3. Set the time at which the PWM waveform should go to 1 in GRA. 4. Set the time at which the PWM waveform should go to 0 in GRB. 5. Set the PWM bit in TMDR to select PWM mode. When PWM mode is selected, regardless of the TIOR contents, GRA and GRB become output compare registers specifying the times at which the PWM goes to 1 and 0. The TIOCA pin automatically becomes the PWM output pin. The TIOCB pin conforms to the settings of bits IOB1 and IOB0 in TIOR. If TIOCB output is not desired, clear both IOB1 and IOB0 to 0. 6. Set the STR bit to 1 in TSTR to start the timer counter. Figure 8.28 Setup Procedure for PWM Mode (Example) Rev.3.00 Mar. 26, 2007 Page 246 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of PWM Mode Figure 8.29 shows examples of operation in PWM mode. The PWM waveform is output from the TIOCA pin. The output goes to 1 at compare match with GRA, and to 0 at compare match with GRB. In the examples shown, TCNT is cleared by compare match with GRA or GRB. Synchronized operation and free-running counting are also possible. TCNT value Counter cleared by compare match with GRA GRA GRB H'0000 Time TIOCA a. Counter cleared by GRA TCNT value Counter cleared by compare match with GRB GRB GRA H'0000 Time TIOCA b. Counter cleared by GRB Figure 8.29 PWM Mode (Example 1) Rev.3.00 Mar. 26, 2007 Page 247 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.30 shows examples of the output of PWM waveforms with duty cycles of 0% and 100%. If the counter is cleared by compare match with GRB, and GRA is set to a higher value than GRB, the duty cycle is 0%. If the counter is cleared by compare match with GRA, and GRB is set to a higher value than GRA, the duty cycle is 100%. TCNT value GRB Counter cleared by compare match with GRB GRA H'0000 Time TIOCA Write to GRA a. 0% duty cycle TCNT value GRA Write to GRA Counter cleared by compare match with GRA GRB H'0000 Time TIOCA Write to GRB Write to GRB b. 100% duty cycle Figure 8.30 PWM Mode (Example 2) Rev.3.00 Mar. 26, 2007 Page 248 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.5 Reset-Synchronized PWM Mode In reset-synchronized PWM mode channels 3 and 4 are combined to produce three pairs of complementary PWM waveforms, all having one waveform transition point in common. When reset-synchronized PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 automatically become PWM output pins, and TCNT3 functions as an up-counter. Table 8.5 lists the PWM output pins. Table 8.6 summarizes the register settings. Table 8.5 Channel 3 Output Pins in Reset-Synchronized PWM Mode Output Pin TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Description PWM output 1 PWM output 1' (complementary waveform to PWM output 1) PWM output 2 PWM output 2' (complementary waveform to PWM output 2) PWM output 3 PWM output 3' (complementary waveform to PWM output 3) 4 Table 8.6 Register TCNT3 TCNT4 GRA3 GRB3 GRA4 GRB4 Register Settings in Reset-Synchronized PWM Mode Setting Initially set to H'0000 Not used (operates independently) Specifies the count period of TCNT3 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4 Rev.3.00 Mar. 26, 2007 Page 249 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Sample Setup Procedure for Reset-Synchronized PWM Mode Figure 8.31 shows a sample procedure for setting up reset-synchronized PWM mode. Reset-synchronized PWM mode Stop counter 1 Select counter clock 2 Select counter clear source 3 Select reset-synchronized PWM mode 4 Set TCNT 5 Set general registers 6 Start counter 7 Reset-synchronized PWM mode 1. Clear the STR3 bit in TSTR to 0 to halt TCNT3. Reset-synchronized PWM mode must be set up while TCNT3 is halted. 2. Set bits TPSC2 to TPSC0 in TCR to select the counter clock source for channel 3. If an external clock source is selected, select the external clock edge(s) with bits CKEG1 and CKEG0 in TCR. 3. Set bits CCLR1 and CCLR0 in TCR3 to select GRA3 compare match as the counter clear source. 4. Set bits CMD1 and CMD0 in TFCR to select reset-synchronized PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and TOCXB4 automatically become PWM output pins. 5. Preset TCNT3 to H'0000. TCNT4 need not be preset. 6. GRA3 is the waveform period register. Set the waveform period value in GRA3. Set transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3. X GRA3 (X: setting value) 7. Set the STR3 bit in TSTR to 1 to start TCNT3. Figure 8.31 Setup Procedure for Reset-Synchronized PWM Mode (Example) Rev.3.00 Mar. 26, 2007 Page 250 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Example of Reset-Synchronized PWM Mode Figure 8.32 shows an example of operation in reset-synchronized PWM mode. TCNT3 operates as an up-counter in this mode. TCNT4 operates independently, detached from GRA4 and GRB4. When TCNT3 matches GRA3, TCNT3 is cleared and resumes counting from H'0000. The PWM outputs toggle at compare match with GRB3, GRA4, GRB4, and TCNT3 respectively, and when the counter is cleared. TCNT3 value Counter cleared at compare match with GRA3 GRA3 GRB3 GRA4 GRB4 H'0000 Time TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 8.32 Operation in Reset-Synchronized PWM Mode (Example) (when OLS3 = OLS4 = 1) For the settings and operation when reset-synchronized PWM mode and buffer mode are both selected, see section 8.4.8, Buffering. Rev.3.00 Mar. 26, 2007 Page 251 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.6 Complementary PWM Mode In complementary PWM mode channels 3 and 4 are combined to output three pairs of complementary, non-overlapping PWM waveforms. When complementary PWM mode is selected TIOCA3, TIOCB3, TIOCA4, TOCXA4, TIOCB4, and TOCXB4 automatically become PWM output pins, and TCNT3 and TCNT4 function as up/downcounters. Table 8.7 lists the PWM output pins. Table 8.8 summarizes the register settings. Table 8.7 Channel 3 Output Pins in Complementary PWM Mode Output Pin TIOCA3 TIOCB3 Description PWM output 1 PWM output 1' (non-overlapping complementary waveform to PWM output 1) PWM output 2 PWM output 2' (non-overlapping complementary waveform to PWM output 2) PWM output 3 PWM output 3' (non-overlapping complementary waveform to PWM output 3) 4 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Table 8.8 Register TCNT3 TCNT4 GRA3 GRB3 GRA4 GRB4 Register Settings in Complementary PWM Mode Setting Initially specifies the non-overlap margin (difference to TCNT4) Initially set to H'0000 Specifies the upper limit value of TCNT3 minus 1 Specifies a transition point of PWM waveforms output from TIOCA3 and TIOCB3 Specifies a transition point of PWM waveforms output from TIOCA4 and TOCXA4 Specifies a transition point of PWM waveforms output from TIOCB4 and TOCXB4 Rev.3.00 Mar. 26, 2007 Page 252 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Setup Procedure for Complementary PWM Mode Figure 8.33 shows a sample procedure for setting up complementary PWM mode. Complementary PWM mode 1. Clear bits STR3 and STR4 to 0 in TSTR to halt the timer counters. Complementary PWM mode must be set up while TCNT3 and TCNT4 are halted. 1 2. Set bits TPSC2 to TPSC0 in TCR to select the same counter clock source for channels 3 and 4. If an external clock source is selected, select the external clock edge(s) with bits CKEG1 and CKEG0 in TCR. Do not select any counter clear source with bits CCLR1 and CCLR0 in TCR. 3. Set bits CMD1 and CMD0 in TFCR to select complementary PWM mode. TIOCA3, TIOCB3, TIOCA4, TIOCB4, TOCXA4, and TOCXB4 automatically become PWM output pins. 4. Clear TCNT4 to H'0000. Set the non-overlap margin in TCNT3. Do not set TCNT3 and TCNT4 to the same value. 5. GRA3 is the waveform period register. Set the upper limit value of TCNT3 minus 1 in GRA3. Set transition times of the PWM output waveforms in GRB3, GRA4, and GRB4. Set times within the compare match range of TCNT3 and TCNT4. T X (X: initial setting of GRB3, GRA4, or GRB4. T: initial setting of TCNT3) 6. Set bits STR3 and STR4 in TSTR to 1 to start TCNT3 and TCNT4. Stop counting Select counter clock 2 Select complementary PWM mode 3 Set TCNTs 4 Set general registers 5 Start counters 6 Complementary PWM mode Note: After exiting complementary PWM mode, to resume operating in complementary PWM mode, follow the entire setup procedure from step 1 again. Figure 8.33 Setup Procedure for Complementary PWM Mode (Example) Rev.3.00 Mar. 26, 2007 Page 253 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Clearing Complementary PWM Mode Figure 8.34 shows a sample procedure for clearing complementary PWM mode. Complementary PWM mode 1. Clear bit CMD1 in TFCR to 0, and set channels 3 and 4 to normal operating mode. 2. After setting channels 3 and 4 to normal operating mode, wait at least one clock count before clearing bits STR3 and STR4 of TSTR to 0 to stop the counter operation of TCNT3 and TCNT4. Clear complementary mode 1 Stop counting 2 Normal operation Figure 8.34 Clearing Procedure for Complementary PWM Mode (Example) Rev.3.00 Mar. 26, 2007 Page 254 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Examples of Complementary PWM Mode Figure 8.35 shows an example of operation in complementary PWM mode. TCNT3 and TCNT4 operate as up/down-counters, counting down from compare match between TCNT3 and GRA3 and counting up from the point at which TCNT4 underflows. During each up-and-down counting cycle, PWM waveforms are generated by compare match with general registers GRB3, GRA4, and GRB4. Since TCNT3 is initially set to a higher value than TCNT4, compare match events occur in the sequence TCNT3, TCNT4, TCNT4, TCNT3. TCNT3 and TCNT4 values GRA3 TCNT3 GRB3 GRA4 GRB4 H'0000 Up-counting starts when TCNT4 underflows TCNT4 Down-counting starts at compare match between TCNT3 and GRA3 Time TIOCA3 TIOCB3 TIOCA4 TOCXA4 TIOCB4 TOCXB4 Figure 8.35 Operation in Complementary PWM Mode (Example 1) (when OLS3 = OLS4 = 1) Rev.3.00 Mar. 26, 2007 Page 255 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.36 shows examples of waveforms with 0% and 100% duty cycles (in one phase) in complementary PWM mode. In this example the outputs change at compare match with GRB3, so waveforms with duty cycles of 0% or 100% can be output by setting GRB3 to a value larger than GRA3. The duty cycle can be changed easily during operation by use of the buffer registers. For further information see section 8.4.8, Buffering. TCNT3 and TCNT4 values GRA3 GRB3 H'0000 TIOCA3 TIOCB3 0% duty cycle a. 0% duty cycle TCNT3 and TCNT4 values GRA3 Time GRB3 H'0000 TIOCA3 TIOCB3 100% duty cycle b. 100% duty cycle Time Figure 8.36 Operation in Complementary PWM Mode (Example 2) (when OLS3 = OLS4 = 1) Rev.3.00 Mar. 26, 2007 Page 256 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) In complementary PWM mode, TCNT3 and TCNT4 overshoot and undershoot at the transitions between up-counting and down-counting. The setting conditions for the IMFA bit in channel 3 and the OVF bit in channel 4 differ from the usual conditions. In buffered operation the buffer transfer conditions also differ. Timing diagrams are shown in figures 8.37 and 8.38. TCNT3 N1 N N+1 N N1 GRA3 N IMFA Set to 1 Buffer transfer signal (BR to GR) Flag not set GR Buffer transfer No buffer transfer Figure 8.37 Overshoot Timing Rev.3.00 Mar. 26, 2007 Page 257 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Underflow TCNT4 H'0001 H'0000 H'FFFF Overflow H'0000 OVF Set to 1 Buffer transfer signal (BR to GR) Flag not set GR Buffer transfer No buffer transfer Figure 8.38 Undershoot Timing In channel 3, IMFA is set to 1 only during up-counting. In channel 4, OVF is set to 1 only when an underflow occurs. When buffering is selected, buffer register contents are transferred to the general register at compare match A3 during up-counting, and when TCNT4 underflows. General Register Settings in Complementary PWM Mode When setting up general registers for complementary PWM mode or changing their settings during operation, note the following points. * Initial settings Do not set values from H'0000 to T - 1 (where T is the initial value of TCNT3). After the counters start and the first compare match A3 event has occurred, however, settings in this range also become possible. * Changing settings Use the buffer registers. Correct waveform output may not be obtained if a general register is written to directly. * Cautions on changes of general register settings Figure 8.39 shows six correct examples and one incorrect example. Rev.3.00 Mar. 26, 2007 Page 258 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) GRA3 GR H'0000 BR Not allowed GR Figure 8.39 Changing a General Register Setting by Buffer Transfer (Example 1) Buffer transfer at transition from up-counting to down-counting If the general register value is in the range from GRA3 - T + 1 to GRA3, do not transfer a buffer register value outside this range. Conversely, if the general register value is outside this range, do not transfer a value within this range. See figure 8.40. GRA3 + 1 GRA3 Illegal changes GRA3 - T + 1 GRA3 - T TCNT3 TCNT4 Figure 8.40 Changing a General Register Setting by Buffer Transfer (Caution 1) Buffer transfer at transition from down-counting to up-counting If the general register value is in the range from H'0000 to T - 1, do not transfer a buffer register value outside this range. Conversely, when a general register value is outside this range, do not transfer a value within this range. See figure 8.41. Rev.3.00 Mar. 26, 2007 Page 259 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) TCNT3 TCNT4 T T-1 Illegal changes H'0000 H'FFFF Figure 8.41 Changing a General Register Setting by Buffer Transfer (Caution 2) General register settings outside the counting range (H'0000 to GRA3) Waveforms with a duty cycle of 0% or 100% can be output by setting a general register to a value outside the counting range. When a buffer register is set to a value outside the counting range, then later restored to a value within the counting range, the counting direction (up or down) must be the same both times. See figure 8.42. GRA3 GR H'0000 0% duty cycle Output pin Output pin 100% duty cycle BR GR Write during down-counting Write during up-counting Figure 8.42 Changing a General Register Setting by Buffer Transfer (Example 2) Settings can be made in this way by detecting GRA3 compare match or TCNT4 underflow before writing to the buffer register. Rev.3.00 Mar. 26, 2007 Page 260 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.7 Phase Counting Mode In phase counting mode the phase difference between two external clock inputs (at the TCLKA and TCLKB pins) is detected, and TCNT2 counts up or down accordingly. In phase counting mode, the TCLKA and TCLKB pins automatically function as external clock input pins and TCNT2 becomes an up/down-counter, regardless of the settings of bits TPSC2 to TPSC0, CKEG1, and CKEG0 in TCR2. Settings of bits CCLR1, CCLR0 in TCR2, and settings in TIOR2, TIER2, TSR2, GRA2, and GRB2 are valid. The input capture and output compare functions can be used, and interrupts can be generated. Phase counting is available only in channel 2. Sample Setup Procedure for Phase Counting Mode Figure 8.43 shows a sample procedure for setting up phase counting mode. Phase counting mode Select phase counting mode 1 Select flag setting condition 2 1. Set the MDF bit in TMDR to 1 to select phase counting mode. 2. Select the flag setting condition with the FDIR bit in TMDR. 3. Set the STR2 bit to 1 in TSTR to start the timer counter. Start counter 3 Phase counting mode Figure 8.43 Setup Procedure for Phase Counting Mode (Example) Rev.3.00 Mar. 26, 2007 Page 261 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Example of Phase Counting Mode Figure 8.44 shows an example of operations in phase counting mode. Table 8.9 lists the upcounting and down-counting conditions for TCNT2. In phase counting mode both the rising and falling edges of TCLKA and TCLKB are counted. The phase difference between TCLKA and TCLKB must be at least 1.5 states, the phase overlap must also be at least 1.5 states, and the pulse width must be at least 2.5 states. See figure 8.45. TCNT2 value Counting up Counting down Time TCLKB TCLKA Figure 8.44 Operation in Phase Counting Mode (Example) Table 8.9 Up/Down Counting Conditions Up-Counting High Low High Low High Low Down-Counting Low High Counting Direction TCLKA pin TCLKB pin Phase difference Phase difference Pulse width Pulse width TCLKA TCLKB Phase difference and overlap: at least 1.5 states Pulse width: at least 2.5 states Overlap Overlap Figure 8.45 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Rev.3.00 Mar. 26, 2007 Page 262 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.8 Buffering Buffering operates differently depending on whether a general register is an output compare register or an input capture register, with further differences in reset-synchronized PWM mode and complementary PWM mode. Buffering is available only in channels 3 and 4. Buffering operations under the conditions mentioned above are described next. * General register used for output compare The buffer register value is transferred to the general register at compare match. See figure 8.46. Compare match signal BR GR Comparator TCNT Figure 8.46 Compare Match Buffering * General register used for input capture The TCNT value is transferred to the general register at input capture. The previous general register value is transferred to the buffer register. See figure 8.47. Input capture signal BR GR TCNT Figure 8.47 Input Capture Buffering * Complementary PWM mode The buffer register value is transferred to the general register when TCNT3 and TCNT4 change counting direction. This occurs at the following two times: When TCNT3 matches GRA3 When TCNT4 underflows * Reset-synchronized PWM mode The buffer register value is transferred to the general register at compare match A3. Rev.3.00 Mar. 26, 2007 Page 263 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Sample Buffering Setup Procedure Figure 8.48 shows a sample buffering setup procedure. Buffering Select general register functions 1 Set buffer bits 2 1. Set TIOR to select the output compare or input capture function of the general registers. 2. Set bits BFA3, BFA4, BFB3, and BFB4 in TFCR to select buffering of the required general registers. 3. Set the STR bits to 1 in TSTR to start the timer counters. Start counters 3 Buffered operation Figure 8.48 Buffering Setup Procedure (Example) Examples of Buffering Figure 8.49 shows an example in which GRA is set to function as an output compare register buffered by BRA, TCNT is set to operate as a periodic counter cleared by GRB compare match, and TIOCA and TIOCB are set to toggle at compare match A and B. Because of the buffer setting, when TIOCA toggles at compare match A, the BRA value is simultaneously transferred to GRA. This operation is repeated each time compare match A occurs. Figure 8.50 shows the transfer timing. Rev.3.00 Mar. 26, 2007 Page 264 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) TCNT value GRB H'0250 H'0200 H'0100 H'0000 BRA GRA TIOCB TIOCA H'0200 H'0250 Counter cleared by compare match B Time H'0100 H'0200 H'0100 H'0200 H'0200 Toggle output Toggle output Compare match A Figure 8.49 Register Buffering (Example 1: Buffering of Output Compare Register) TCNT Compare match signal Buffer transfer signal BR GR n N N n n+1 Figure 8.50 Compare Match and Buffer Transfer Timing (Example) Rev.3.00 Mar. 26, 2007 Page 265 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.51 shows an example in which GRA is set to function as an input capture register buffered by BRA, and TCNT is cleared by input capture B. The falling edge is selected as the input capture edge at TIOCB. Both edges are selected as input capture edges at TIOCA. Because of the buffer setting, when the TCNT value is captured into GRA at input capture A, the previous GRA value is simultaneously transferred to BRA. Figure 8.52 shows the transfer timing. TCNT value H'0180 H'0160 Counter cleared by input capture B H'0005 H'0000 TIOCB Time TIOCA GRA H'0005 H'0160 BRA H'0005 H'0160 GRB H'0180 Input capture A Figure 8.51 Register Buffering (Example 2: Buffering of Input Capture Register) Rev.3.00 Mar. 26, 2007 Page 266 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) TIOC pin Input capture signal TCNT GR BR M m n n M n+1 N n M N n N+1 Figure 8.52 Input Capture and Buffer Transfer Timing (Example) Rev.3.00 Mar. 26, 2007 Page 267 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Figure 8.53 shows an example in which GRB3 is buffered by BRB3 in complementary PWM mode. Buffering is used to set GRB3 to a higher value than GRA3, generating a PWM waveform with 0% duty cycle. The BRB3 value is transferred to GRB3 when TCNT3 matches GRA3, and when TCNT4 underflows. TCNT3 and TCNT4 values H'1FFF GRA3 TCNT3 TCNT4 GRB3 H'0999 H'0000 Time BRB3 GRB3 H'0999 H'0999 H'0999 H'1FFF H'1FFF H'1FFF H'0999 H'0999 TIOCA3 TIOCB3 Figure 8.53 Register Buffering (Example 4: Buffering in Complementary PWM Mode) Rev.3.00 Mar. 26, 2007 Page 268 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.4.9 ITU Output Timing The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external trigger, or inverted by bit settings in TOCR. Timing of Enabling and Disabling of ITU Output by TOER In this example an ITU output is disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by appropriate settings of the data register (DR) and data direction register (DDR) of the corresponding input/output port. Figure 8.54 illustrates the timing of the enabling and disabling of ITU output by TOER. T1 T2 T3 Address TOER address TOER ITU output pin Timer output I/O port ITU output Generic input/output Figure 8.54 Timing of Disabling of ITU Output by Writing to TOER (Example) Rev.3.00 Mar. 26, 2007 Page 269 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Timing of Disabling of ITU Output by External Trigger If the XTGD bit is cleared to 0 in TOCR in reset-synchronized PWM mode or complementary PWM mode, when an input capture A signal occurs in channel 1, the master enable bits are cleared to 0 in TOER, disabling ITU output. Figure 8.55 shows the timing. TIOCA1 pin Input capture signal TOER ITU output pins N ITU output ITU output Legend: N: Arbitrary setting (H'C1 to H'FF) H'C0 I/O port Generic input/output N ITU output ITU output H'C0 I/O port Generic input/output Figure 8.55 Timing of Disabling of ITU Output by External Trigger (Example) Rev.3.00 Mar. 26, 2007 Page 270 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Timing of Output Inversion by TOCR The output levels in reset-synchronized PWM mode and complementary PWM mode can be inverted by inverting the output level select bits (OLS4 and OLS3) in TOCR. Figure 8.56 shows the timing. T1 T2 T3 Address TOCR address TOCR ITU output pin Inverted Figure 8.56 Timing of Inverting of ITU Output Level by Writing to TOCR (Example) Rev.3.00 Mar. 26, 2007 Page 271 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.5 Interrupts The ITU has two types of interrupts: input capture/compare match interrupts, and overflow interrupts. 8.5.1 Setting of Status Flags Timing of Setting of IMFA and IMFB at Compare Match IMFA and IMFB are set to 1 by a compare match signal generated when TCNT matches a general register (GR). The compare match signal is generated in the last state in which the values match (when TCNT is updated from the matching count to the next count). Therefore, when TCNT matches a general register, the compare match signal is not generated until the next timer clock input. Figure 8.57 shows the timing of the setting of IMFA and IMFB. TCNT input clock TCNT N N+1 GR N Compare match signal IMF IMI Figure 8.57 Timing of Setting of IMFA and IMFB by Compare Match Rev.3.00 Mar. 26, 2007 Page 272 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Timing of Setting of IMFA and IMFB by Input Capture IMFA and IMFB are set to 1 by an input capture signal. The TCNT contents are simultaneously transferred to the corresponding general register. Figure 8.58 shows the timing. Input capture signal IMF TCNT N GR N IMI Figure 8.58 Timing of Setting of IMFA and IMFB by Input Capture Timing of Setting of Overflow Flag (OVF) OVF is set to 1 when TCNT overflows from H'FFFF to H'0000 or underflows from H'0000 to H'FFFF. Figure 8.59 shows the timing. Rev.3.00 Mar. 26, 2007 Page 273 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) TCNT H'FFFF H'0000 Overflow signal OVF OVI Figure 8.59 Timing of Setting of OVF 8.5.2 Clearing of Status Flags If the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 8.60 shows the timing. TSR write cycle T1 T2 T3 Address TSR address IMF, OVF Figure 8.60 Timing of Clearing of Status Flags Rev.3.00 Mar. 26, 2007 Page 274 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.5.3 Interrupt Sources Each ITU channel can generate a compare match/input capture A interrupt, a compare match/input capture B interrupt, and an overflow interrupt. In total there are 15 interrupt sources, all independently vectored. An interrupt is requested when the interrupt request flag and interrupt enable bit are both set to 1. The priority order of the channels can be modified in interrupt priority registers A and B (IPRA and IPRB). For details see section 5, Interrupt Controller. Table 8.10 lists the interrupt sources. Table 8.10 ITU Interrupt Sources Channel 0 Interrupt Source IMIA0 IMIB0 OVI0 1 IMIA1 IMIB1 OVI1 2 IMIA2 IMIB2 OVI2 3 IMIA3 IMIB3 OVI3 4 IMIA4 IMIB4 OVI4 Note: * Description Compare match/input capture A0 Compare match/input capture B0 Overflow 0 Compare match/input capture A1 Compare match/input capture B1 Overflow 1 Compare match/input capture A2 Compare match/input capture B2 Overflow 2 Compare match/input capture A3 Compare match/input capture B3 Overflow 3 Compare match/input capture A4 Compare match/input capture B4 Overflow 4 Low Priority* High The priority immediately after a reset is indicated. Inter-channel priorities can be changed by settings in IPRA and IPRB. Rev.3.00 Mar. 26, 2007 Page 275 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) 8.6 Usage Notes This section describes contention and other matters requiring special attention during ITU operations. Contention between TCNT Write and Clear If a counter clear signal occurs in the T3 state of a TCNT write cycle, clearing of the counter takes priority and the write is not performed. See figure 8.61. TCNT write cycle T1 T2 T3 Address TCNT address Internal write signal Counter clear signal TCNT N H'0000 Figure 8.61 Contention between TCNT Write and Clear Rev.3.00 Mar. 26, 2007 Page 276 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Word Write and Increment If an increment pulse occurs in the T3 state of a TCNT word write cycle, writing takes priority and TCNT is not incremented. See figure 8.62. TCNT word write cycle T1 T2 T3 Address TCNT address Internal write signal TCNT input clock TCNT N M TCNT write data Figure 8.62 Contention between TCNT Word Write and Increment Rev.3.00 Mar. 26, 2007 Page 277 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Byte Write and Increment If an increment pulse occurs in the T2 or T3 state of a TCNT byte write cycle, writing takes priority and TCNT is not incremented. The TCNT byte that was not written retains its previous value. See figure 8.63, which shows an increment pulse occurring in the T2 state of a byte write to TCNTH. TCNTH byte write cycle T1 T2 T3 Address TCNTH address Internal write signal TCNT input clock TCNTH N TCNT write data M TCNTL X X+1 X Figure 8.63 Contention between TCNT Byte Write and Increment Rev.3.00 Mar. 26, 2007 Page 278 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between General Register Write and Compare Match If a compare match occurs in the T3 state of a general register write cycle, writing takes priority and the compare match signal is inhibited. See figure 8.64. General register write cycle T1 T2 T3 Address GR address Internal write signal TCNT N N+1 GR N M General register write data Compare match signal Inhibited Figure 8.64 Contention between General Register Write and Compare Match Rev.3.00 Mar. 26, 2007 Page 279 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between TCNT Write and Overflow or Underflow If an overflow occurs in the T3 state of a TCNT write cycle, writing takes priority and the counter is not incremented. OVF is set to 1. The same holds for underflow. See figure 8.65. TCNT write cycle T1 T2 T3 Address TCNT address Internal write signal TCNT input clock Overflow signal TCNT H'FFFF TCNT write data M OVF Figure 8.65 Contention between TCNT Write and Overflow Rev.3.00 Mar. 26, 2007 Page 280 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between General Register Read and Input Capture If an input capture signal occurs during the T3 state of a general register read cycle, the value before input capture is read. See figure 8.66. General register read cycle T1 T2 T3 Address GR address Internal read signal Input capture signal GR X M Internal data bus X Figure 8.66 Contention between General Register Read and Input Capture Rev.3.00 Mar. 26, 2007 Page 281 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between Counter Clearing by Input Capture and Counter Increment If an input capture signal and counter increment signal occur simultaneously, the counter is cleared according to the input capture signal. The counter is not incremented by the increment signal. The value before the counter is cleared is transferred to the general register. See figure 8.67. Input capture signal Counter clear signal TCNT input clock TCNT N H'0000 GR N Figure 8.67 Contention between Counter Clearing by Input Capture and Counter Increment Rev.3.00 Mar. 26, 2007 Page 282 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between General Register Write and Input Capture If an input capture signal occurs in the T3 state of a general register write cycle, input capture takes priority and the write to the general register is not performed. See figure 8.68. General register write cycle T1 T2 T3 Address GR address Internal write signal Input capture signal TCNT M GR M Figure 8.68 Contention between General Register Write and Input Capture Note on Waveform Period Setting When a counter is cleared by compare match, the counter is cleared in the last state at which the TCNT value matches the general register value, at the time when this value would normally be updated to the next count. The actual counter frequency is therefore given by the following formula: f= (N + 1) (f: counter frequency. : system clock frequency. N: value set in general register.) Rev.3.00 Mar. 26, 2007 Page 283 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Contention between Buffer Register Write and Input Capture If a buffer register is used for input capture buffering and an input capture signal occurs in the T3 state of a write cycle, input capture takes priority and the write to the buffer register is not performed. See figure 8.69. Buffer register write cycle T1 T2 T3 Address BR address Internal write signal Input capture signal GR N X TCNT value BR M N Figure 8.69 Contention between Buffer Register Write and Input Capture Rev.3.00 Mar. 26, 2007 Page 284 of 682 REJ09B0353-0300 Section 8 16-Bit Integrated Timer Unit (ITU) Note on Synchronous Preset When channels are synchronized, if a TCNT value is modified by byte write access, all 16 bits of all synchronized counters assume the same value as the counter that was addressed. (Example) When channels 2 and 3 are synchronized * Byte write to channel 2 or byte write to channel 3 Write A to upper byte of channel 2 TCNT2 TCNT3 W Y X Z TCNT2 TCNT3 A A X X Upper byte Lower byte Write A to lower byte of channel 3 TCNT2 TCNT3 Upper byte Lower byte Y Y A A Upper byte Lower byte * Word write to channel 2 or word write to channel 3 TCNT2 TCNT3 W Y X Z Write AB word to channel 2 or 3 TCNT2 TCNT3 A A B B Upper byte Lower byte Upper byte Lower byte Note on Setup of Reset-Synchronized PWM Mode and Complementary PWM Mode When setting bits CMD1 and CMD0 in TFCR, take the following precautions: * Write to bits CMD1 and CMD0 only when TCNT3 and TCNT4 are stopped. * Do not switch directly between reset-synchronized PWM mode and complementary PWM mode. First switch to normal mode (by clearing bit CMD1 to 0), then select reset-synchronized PWM mode or complementary PWM mode. Rev.3.00 Mar. 26, 2007 Page 285 of 682 REJ09B0353-0300 Register Settings TMDR TFCR TOCR TOER TIOR0 TCR0 TSNC Operating Mode MDF -- -- -- -- PWM0 = 0 -- -- -- -- -- -- IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted CCLR1 = 0 CCLR0 = 1 -- CCLR1 = 1 CCLR0 = 0 -- -- CCLR1 = 1 CCLR0 = 1 -- PWM0 = 1 -- -- -- -- -- -- -- * -- -- -- -- -- -- -- FDIR IOA PWM IOB Output Master Level Enable Select Clear Select Clock Select Synchronization ResetComple- SynchroBuffermentary XTGD nized ing PWM PWM Synchronous preset SYNC0 = 1 PWM mode ITU Operating Modes Output compare A Output compare B -- -- -- -- -- -- -- -- Input capture A -- -- PWM0 = 0 -- -- -- -- -- -- Rev.3.00 Mar. 26, 2007 Page 286 of 682 REJ09B0353-0300 -- -- PWM0 = 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Section 8 16-Bit Integrated Timer Unit (ITU) Input capture B Table 8.11 (a) ITU Operating Modes (Channel 0) Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear SYNC0 = 1 Legend: : Setting available (valid). --: Setting does not affect this mode. Note: The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Register Settings TMDR TFCR TOCR TOER TIOR1 TCR1 TSNC Operating Mode MDF IOA IOB FDIR XTGD PWM Output Level Select Master Enable Clear Select -- -- -- IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted -- CCLR1 = 0 CCLR0 = 1 -- -- CCLR1 = 1 CCLR0 = 0 -- -- -- CCLR1 = 1 CCLR0 = 1 -- *1 -- -- -- Synchronization -- -- -- -- PWM1 = 0 -- -- -- -- -- PWM1 = 1 -- -- -- -- -- -- -- -- -- ResetComple- SynchroBuffermentary nized ing PWM PWM Clock Select Synchronous preset SYNC1 = 1 PWM mode Output compare A Output compare B -- -- -- -- -- -- -- -- Input capture A -- -- PWM1 = 0 -- -- -- *2 -- -- Input capture B -- -- PWM1 = 0 -- -- -- -- -- -- Table 8.11 (b) ITU Operating Modes (Channel 1) Counter By compare clearing match/input capture A -- -- -- -- -- -- -- -- -- -- -- -- -- By compare match/input capture B -- -- -- -- -- Synchronous clear SYNC1 = 1 Section 8 16-Bit Integrated Timer Unit (ITU) Rev.3.00 Mar. 26, 2007 Page 287 of 682 REJ09B0353-0300 Legend: : Setting available (valid). --: Setting does not affect this mode. Notes: 1. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. 2. Valid only when channels 3 and 4 are operating in complementary PWM mode or reset-synchronized PWM mode. Register Settings TMDR TFCR TOCR TOER TIOR2 TCR2 TSNC Operating Mode MDF FDIR PWM ResetOutput CompleMaster Synchro- Buffermentary XTGD Level Enable nized ing Select PWM PWM IOA IOB Clear Select Clock Select -- PWM2 = 1 PWM2 = 0 -- -- -- -- -- -- IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted IOA2 = 1 Other bits unrestricted IOB2 = 1 Other bits unrestricted -- CCLR1 = 0 CCLR0 = 1 -- -- CCLR1 = 1 CCLR0 = 0 -- -- -- CCLR1 = 1 CCLR0 = 1 -- -- -- -- -- -- -- -- -- -- -- -- * -- -- -- -- -- Synchronization -- -- -- Synchronous preset SYNC2 = 1 PWM mode Output compare A Output compare B -- -- -- -- -- -- -- Rev.3.00 Mar. 26, 2007 Page 288 of 682 REJ09B0353-0300 -- PWM2 = 0 -- -- -- -- -- -- -- PWM2 = 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MDF = 1 -- -- Input capture A Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.11 (c) ITU Operating Modes (Channel 2) Input capture B Counter By compare clearing match/input capture A By compare match/input capture B Synchronous clear SYNC2 = 1 Phase counting mode Legend: : Setting available (valid). --: Setting does not affect this mode. Note: The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously , the compare match signal is inhibited. TSNC MDF *1 -- IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted *2 -- -- -- PWM3 = 1 CMD1 = 0 PWM3 = 0 CMD1 = 0 -- -- -- FDIR PWM Complementary PWM *3 Master Enable IOA IOB Clear Select Clock Select TMDR TOER TIOR3 TCR3 Operating Mode Synchronization Synchronous preset PWM mode Output compare A SYNC3 = 1 Register Settings TFCR TOCR ResetOutput Synchro- Buffering XTGD Level nized PWM Select -- -- CMD1 = 0 -- -- CMD1 = 0 -- -- Output compare B -- -- CMD1 = 0 CMD1 = 0 -- -- Input capture A -- -- PWM3 = 0 CMD1 = 0 CMD1 = 0 -- -- Input capture B -- -- PWM3 = 0 CMD1 = 0 CMD1 = 0 -- -- Counter clearing -- -- -- -- -- -- -- -- EA3 ignored IOA2 = 1 Other bits Other bits unrestricted unrestricted EB3 ignored IOB2 = 1 Other bits Other bits unrestricted unrestricted *1 CCLR1 = 0 CCLR0 = 1 *1 CCLR1 = 1 CCLR0 = 0 *1 CCLR1 = 1 CCLR0 = 1 *4 Illegal setting: CMD1 = 1 CMD0 = 0 CMD1 = 0 CMD1 = 0 Table 8.11 (d) ITU Operating Modes (Channel 3) -- -- -- -- -- -- -- -- -- -- -- -- *6 *6 -- -- *1 -- -- -- -- By compare match/input capture A By compare match/input capture B SynSYNC3 = 1 chronous clear *3 Complementary PWM mode Reset-synchronized PWM mode Buf fering (BRA) Illegal setting: CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 -- -- BFA3 = 1 Other bits unrestricted BFB3 = 1 Other bits unrestricted -- -- CCLR1 = 0 CCLR0 = 0 CCLR1 = 0 CCLR0 = 1 *5 Buffering (BRB) *1 Section 8 16-Bit Integrated Timer Unit (ITU) Rev.3.00 Mar. 26, 2007 Page 289 of 682 REJ09B0353-0300 Legend: Notes: 1. 2. 3. 4. 5. 6. : Setting available (valid). --: Setting does not affect this mode. Master enable bit settings are valid only during waveform output. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected. The counter cannot be cleared by input capture A when reset-synchronized PWM mode is selected. In complementary PWM mode, select the same clock source for channels 3 and 4. Use the input capture A function in channel 1. Operating Mode MDF *1 -- IOA2 = 0 Other bits unrestricted IOB2 = 0 Other bits unrestricted *2 -- -- -- PWM4 = 1 CMD1 = 0 PWM4 = 0 CMD1 = 0 -- -- -- FDIR PWM Complementary PWM *3 Master Enable IOA IOB Clear Select Clock Select TSNC TMDR TOER TIOR4 TCR4 Synchronization Synchronous preset PWM mode Output compare A SYNC4 = 1 Register Settings TFCR TOCR ResetOutput Synchro- Buffering XTGD Level nized PWM Select -- -- CMD1 = 0 -- -- CMD1 = 0 -- -- Output compare B -- -- CMD1 = 0 CMD1 = 0 -- -- Input capture A -- -- PWM4 = 0 CMD1 = 0 CMD1 = 0 -- -- Input capture B -- -- PWM4 = 0 CMD1 = 0 CMD1 = 0 -- -- Rev.3.00 Mar. 26, 2007 Page 290 of 682 REJ09B0353-0300 -- -- *4 -- -- EA4 ignored IOA2 = 1 Other bits Other bits unrestricted unrestricted EB4 ignored IOB2 = 1 Other bits Other bits unrestricted unrestricted *1 CCLR1 = 0 CCLR0 = 1 *1 CCLR1 = 1 CCLR0 = 0 *1 -- CCLR1 = 1 CCLR0 = 1 -- -- -- -- *1 -- -- CCLR1 = 0 CCLR0 = 0 *6 *5 *6 -- -- *4 -- -- -- -- *4 -- -- -- -- -- -- -- -- -- Illegal setting: CMD1 = 1 CMD0 = 0 Illegal setting: CMD1 = 1 CMD0 = 0 Illegal setting: CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 CMD1 = 1 CMD0 = 0 CMD1 = 1 CMD0 = 1 -- -- BFA4 = 1 Other bits unrestricted BFB4 = 1 Other bits unrestricted -- -- *1 Section 8 16-Bit Integrated Timer Unit (ITU) Table 8.11 (e) ITU Operating Modes (Channel 4) Counter By compare clearing match/input capture A By compare match/input capture B SynSYNC4 = 1 chronous clear *3 Complementary PWM mode Reset-synchronized PWM mode Buffering (BRA) Buffering (BRB) Legend: Notes: 1. 2. 3. 4. 5. 6. : Setting available (valid). --: Setting does not affect this mode. Master enable bit settings are valid only during waveform output. The input capture function cannot be used in PWM mode. If compare match A and compare match B occur simultaneously, the compare match signal is inhibited. Do not set both channels 3 and 4 for synchronous operation when complementary PWM mode is selected. When reset-synchronized PWM mode is selected, TCNT4 operates independently and the counter clearing function is available. W aveform output is not affected. In complementary PWM mode, select the same clock source for channels 3 and 4. TCR4 settings are valid in reset-synchronized PWM mode, but TCNT4 operates independently , without affecting waveform output. Section 9 Programmable Timing Pattern Controller Section 9 Programmable Timing Pattern Controller 9.1 Overview The H8/3039 Group has a built-in programmable timing pattern controller (TPC)* that provides pulse outputs by using the 16-bit integrated timer-pulse unit (ITU) as a time base. The TPC pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate simultaneously and independently. 9.1.1 Features TPC features are listed below. * 15-bit output data Maximum 15-bit data can be output. TPC output can be enabled on a bit-by-bit basis. * Four output groups and one 3-bit output. Output trigger signals can be selected in 4-bit groups to provide up to three different 4-bit outputs and one 3-bit output. * Selectable output trigger signals Output trigger signals can be selected for each group from the compare-match signals of four ITU channels. * Non-overlap mode A non-overlap margin can be provided between pulse outputs. Note: * Note that since this LSI does not have a TP14 pin, it is a 15-bit programmable timing pattern controller (TPC). Rev.3.00 Mar. 26, 2007 Page 291 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.1.2 Block Diagram Figure 9.1 shows a block diagram of the TPC. ITU compare match signals PADDR Control logic NDERA TPMR PBDDR NDERB TPCR TP15 (TP14)* TP13 TP12 TP11 TP10 TP9 TP8 TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 Legend: TPMR: TPCR: NDERB: NDERA: PBDDR: PADDR: NDRB: NDRA: PBDR: PADR: Pulse output pins, group 3 PBDR Pulse output pins, group 2 NDRB Internal data bus Pulse output pins, group 1 PADR Pulse output pins, group 0 NDRA TPC output mode register TPC output control register Next data enable register B Next data enable register A Port B data direction register Port A data direction register Next data register B Next data register A Port B data register Port A data register Note: * Since this LSI does not have this pin, this signal cannot be output to the outside. Figure 9.1 TPC Block Diagram Rev.3.00 Mar. 26, 2007 Page 292 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.1.3 TPC Pins Table 9.1 summarizes the TPC output pins. Table 9.1 Name TPC output 0 TPC output 1 TPC output 2 TPC output 3 TPC output 4 TPC output 5 TPC output 6 TPC output 7 TPC output 8 TPC output 9 TPC output 10 TPC output 11 TPC output 12 TPC output 13 (TPC output 14)* TPC output 15 Note: * TPC Pins Symbol TP0 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 (TP14)* TP15 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output (Output)* Output Group 3 pulse output Group 2 pulse output Group 1 pulse output Function Group 0 pulse output Since this LSI does not have this pin, this signal cannot be output to the outside. Rev.3.00 Mar. 26, 2007 Page 293 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.1.4 Registers Table 9.2 summarizes the TPC registers. Table 9.2 Address* H'FFD1 H'FFD3 H'FFD4 H'FFD6 H'FFA0 H'FFA1 H'FFA2 H'FFA3 H'FFA5/ 3 H'FFA7* H'FFA4/ 3 H'FFA6* 1 TPC Registers Name Port A data direction register Port A data register Port B data direction register Port B data register TPC output mode register TPC output control register Next data enable register B Next data enable register A Next data register A Next data register B Abbreviation PADDR PADR PBDDR PBDR TPMR TPCR NDERB NDERA NDRA NDRB R/W W R/(W)* W R/(W)* R/W R/W R/W R/W R/W R/W 2 2 Initial Value H'00 H'00 H'00 H'00 H'F0 H'FF H'00 H'00 H'00 H'00 Notes: 1. Lower 16 bits of the address. 2. Bits used for TPC output cannot be written. 3. The NDRA address is H'FFA5 when the same output trigger is selected for TPC output groups 0 and 1 by settings in TPCR. When the output triggers are different, the NDRA address is H'FFA7 for group 0 and H'FFA5 for group 1. Similarly, the address of NDRB is H'FFA4 when the same output trigger is selected for TPC output groups 2 and 3 by settings in TPCR. When the output triggers are different, the NDRB address is H'FFA6 for group 2 and H'FFA4 for group 3. Rev.3.00 Mar. 26, 2007 Page 294 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2 9.2.1 Register Descriptions Port A Data Direction Register (PADDR) PADDR is an 8-bit write-only register that selects input or output for each pin in port A. Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR Port A data direction 7 to 0 These bits select input or output for port A pins Port A is multiplexed with pins TP7 to TP0. Bits corresponding to pins used for TPC output must be set to 1. For further information about PADDR, see section 7.10, Port A. 9.2.2 Port A Data Register (PADR) PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when these TPC output groups are used. Bit Initial value Read/Write 7 PA 7 0 R/(W)* 6 PA 6 0 R/(W)* 5 PA 5 0 R/(W)* 4 PA 4 0 R/(W)* 3 PA 3 0 R/(W)* 2 PA 2 0 R/(W)* 1 PA 1 0 R/(W)* 0 PA 0 0 R/(W)* Port A data 7 to 0 These bits store output data for TPC output groups 0 and 1 Note: * Bits selected for TPC output by NDERA settings become read-only bits. For further information about PADR, see section 7.10, Port A. Rev.3.00 Mar. 26, 2007 Page 295 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2.3 Port B Data Direction Register (PBDDR) PBDDR is an 8-bit write-only register that selects input or output for each pin in port B. Bit Initial value Read/Write 7 PB7 DDR 0 W 6 -- 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Reserved bit Port B data direction 7, 5 to 0 These bits select input or output for port B pins Port B is multiplexed with pins TP15, TP13 to TP8. Bits corresponding to pins used for TPC output must be set to 1. For further information about PBDDR, see section 7.11, Port B. 9.2.4 Port B Data Register (PBDR) PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when these TPC output groups are used. Bit Initial value Read/Write 7 PB 7 0 R/(W)* 6 -- 0 R/(W)* 5 PB 5 0 R/(W)* 4 PB 4 0 R/(W)* 3 PB 3 0 R/(W)* 2 PB 2 0 R/(W)* 1 PB 1 0 R/(W)* 0 PB 0 0 R/(W)* Reserved bit Port B data 7, 5 to 0 These bits store output data for TPC output groups 2 and 3 Note: * Bits selected for TPC output by NDERB settings become read-only bits. For further information about PBDR, see section 7.11, Port B. Rev.3.00 Mar. 26, 2007 Page 296 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2.5 Next Data Register A (NDRA) NDRA is an 8-bit readable/writable register that stores the next output data for TPC output groups 1 and 0 (pins TP7 to TP0). During TPC output, when an ITU compare match event specified in TPCR occurs, NDRA contents are transferred to the corresponding bits in PADR. The address of NDRA differs depending on whether TPC output groups 0 and 1 have the same output trigger or different output triggers. NDRA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Same Trigger for TPC Output Groups 0 and 1 If TPC output groups 0 and 1 are triggered by the same compare match event, the NDRA address is H'FFA5. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FFA7 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next data 7 to 4 These bits store the next output data for TPC output group 1 Next data 3 to 0 These bits store the next output data for TPC output group 0 Address H'FFA7 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Reserved bits Rev.3.00 Mar. 26, 2007 Page 297 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Different Triggers for TPC Output Groups 0 and 1 If TPC output groups 0 and 1 are triggered by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFA5 and the address of the lower 4 bits (group 0) is H'FFA7. Bits 3 to 0 of address H'FFA5 and bits 7 to 4 of address H'FFA7 are reserved bits that cannot be modified and always read 1. Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Next data 7 to 4 These bits store the next output data for TPC output group 1 Reserved bits Address H'FFA7 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Reserved bits Next data 3 to 0 These bits store the next output data for TPC output group 0 Rev.3.00 Mar. 26, 2007 Page 298 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2.6 Next Data Register B (NDRB) NDRB is an 8-bit readable/writable register that stores the next output data for TPC output groups 3 and 2 (pins TP15 to TP8)*. During TPC output, when an ITU compare match event specified in TPCR occurs, NDRB contents are transferred to the corresponding bits in PBDR. The address of NDRB differs depending on whether TPC output groups 2 and 3 have the same output trigger or different output triggers. NDRB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside. Same Trigger for TPC Output Groups 2 and 3 If TPC output groups 2 and 3 are triggered by the same compare match event, the NDRB address is H'FFA4. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FFA6 consists entirely of reserved bits that cannot be modified and always read 1. Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Next data 15 to 12 These bits store the next output data for TPC output group 3 Next data 11 to 8 These bits store the next output data for TPC output group 2 Address H'FFA6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Reserved bits Rev.3.00 Mar. 26, 2007 Page 299 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Different Triggers for TPC Output Groups 2 and 3 If TPC output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits of NDRB (group 3)* is H'FFA4 and the address of the lower 4 bits (group 2) is H'FFA6. Bits 3 to 0 of address H'FFA4 and bits 7 to 4 of address H'FFA6 are reserved bits that cannot be modified and always read 1. Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip. Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Next data 15 to 12 These bits store the next output data for TPC output group 3 Reserved bits Address H'FFA6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Reserved bits Next data 11 to 8 These bits store the next output data for TPC output group 2 Rev.3.00 Mar. 26, 2007 Page 300 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2.7 Next Data Enable Register A (NDERA) NDERA is an 8-bit readable/writable register that enables or disables TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bit Initial value Read/Write 7 NDER7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0 R/W NDER6 NDER5 NDER4 NDER3 NDER1 NDER0 Next data enable 7 to 0 These bits enable or disable TPC output groups 1 and 0 If a bit is enabled for TPC output by NDERA, then when the ITU compare match event selected in the TPC output control register (TPCR) occurs, the NDRA value is automatically transferred to the corresponding PADR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRA to PADR and the output value does not change. NDERA is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable TPC output groups 1 and 0 (TP7 to TP0) on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 0 1 Description TPC outputs TP7 to TP0 are disabled (NDR7 to NDR0 are not transferred to PA7 to PA0) TPC outputs TP7 to TP0 are enabled (NDR7 to NDR0 are transferred to PA7 to PA0) (Initial value) Rev.3.00 Mar. 26, 2007 Page 301 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2.8 Next Data Enable Register B (NDERB) NDERB is an 8-bit readable/writable register that enables or disables TPC output groups 3 and 2 (TP15 to TP8)* on a bit-by-bit basis. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Next data enable 15 to 8 These bits enable or disable TPC output groups 3 and 2 If a bit is enabled for TPC output by NDERB, then when the ITU compare match event selected in the TPC output control register (TPCR) occurs, the NDRB value is automatically transferred to the corresponding PBDR bit, updating the output value. If TPC output is disabled, the bit value is not transferred from NDRB to PBDR and the output value does not change. NDERB is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0--Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable TPC output groups 3 and 2 (TP15 to TP8)* on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 0 1 Description TPC outputs TP15 to TP8 are disabled (NDR15 to NDR8 are not transferred to PB7 to PB0) TPC outputs TP15 to TP8 are enabled (NDR15 to NDR8 are transferred to PB7 to PB0) (Initial value) Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside. Rev.3.00 Mar. 26, 2007 Page 302 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2.9 TPC Output Control Register (TPCR) TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a group-by-group basis. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Group 3 compare match select 1 and 0 These bits select the compare match Group 2 compare event that triggers match select 1 and 0 TPC output group 3 These bits select (TP15 to TP12)* the compare match Group 1 compare event that triggers match select 1 and 0 TPC output group 2 These bits select (TP11 to TP8) the compare match Group 0 compare event that triggers match select 1 and 0 TPC output group 1 These bits select (TP7 to TP4) the compare match event that triggers TPC output group 0 (TP3 to TP0) Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside. TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Rev.3.00 Mar. 26, 2007 Page 303 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match event that triggers TPC output group 3 (TP15 to TP12)*. Bit 7 G3CMS1 0 Bit6 G3CMS0 0 1 1 0 1 Note: * Description TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 0 TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 1 TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 2 TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 3 (Initial value) Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip. Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match event that triggers TPC output group 2 (TP11 to TP8). Bit 5 G2CMS1 0 Bit4 G2CMS0 0 1 1 0 1 Description TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 2 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 3 (Initial value) Rev.3.00 Mar. 26, 2007 Page 304 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match event that triggers TPC output group 1 (TP7 to TP4). Bit 3 G1CMS1 0 Bit2 G1CMS0 0 1 1 0 1 Description TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 2 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 3 (Initial value) Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match event that triggers TPC output group 0 (TP3 to TP0). Bit1 G0CMS1 0 Bit0 G0CMS0 0 1 1 0 1 Description TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 2 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 3 (Initial value) Rev.3.00 Mar. 26, 2007 Page 305 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.2.10 TPC Output Mode Register (TPMR) TPMR is an 8-bit readable/writable register that selects normal or non-overlapping TPC output for each group. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W G3NOV G2NOV G1NOV G0NOV Reserved bits Group 3 non-overlap Selects non-overlapping TPC output for group 3 (TP15 to TP12)* Group 2 non-overlap Selects non-overlapping TPC output for group 2 (TP11 to TP8 ) Group 1 non-overlap Selects non-overlapping TPC output for group 1 (TP7 to TP4 ) Group 0 non-overlap Selects non-overlapping TPC output for group 0 (TP3 to TP0 ) Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside. The output trigger period of a non-overlapping TPC output waveform is set in general register B (GRB) in the ITU channel selected for output triggering. The non-overlap margin is set in general register A (GRA). The output values change at compare match A and B. For details see section 9.3.4, Non-Overlapping TPC Output. TPMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 306 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Bit 3--Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping TPC output for group 3 (TP15 to TP12)*. Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip. Bit 3 G3NOV 0 1 Description Normal TPC output in group 3 (output values change at compare match A in the selected ITU channel) (Initial value) Non-overlapping TPC output in group 3 (independent 1 and 0 output at compare match A and B in the selected ITU channel) Bit 2--Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping TPC output for group 2 (TP11 to TP8). Bit 2 G2NOV 0 1 Description Normal TPC output in group 2 (output values change at compare match A in the selected ITU channel) (Initial value) Non-overlapping TPC output in group 2 (independent 1 and 0 output at compare match A and B in the selected ITU channel) Bit 1--Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping TPC output for group 1 (TP7 to TP4). Bit 1 G1NOV 0 1 Description Normal TPC output in group 1 (output values change at compare match A in the selected ITU channel) (Initial value) Non-overlapping TPC output in group 1 (independent 1 and 0 output at compare match A and B in the selected ITU channel) Rev.3.00 Mar. 26, 2007 Page 307 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Bit 0--Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping TPC output for group 0 (TP3 to TP0). Bit 0 G0NOV 0 1 Description Normal TPC output in group 0 (output values change at compare match A in the selected ITU channel) (Initial value) Non-overlapping TPC output in group 0 (independent 1 and 0 output at compare match A and B in the selected ITU channel) 9.3 9.3.1 Operation Overview When corresponding bits in PADDR or PBDDR and NDERA or NDERB are set to 1, TPC output is enabled. The TPC output initially consists of the corresponding PADR or PBDR contents. When a compare-match event selected in TPCR occurs, the corresponding NDRA or NDRB bit contents are transferred to PADR or PBDR to update the output values. Figure 9.2 illustrates the TPC output operation. Table 9.3 summarizes the TPC operating conditions. DDR Q NDER Q Output trigger signal C Q TPC output pin DR D Q NDR D Internal data bus Figure 9.2 TPC Output Operation Rev.3.00 Mar. 26, 2007 Page 308 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Table 9.3 NDER 0 TPC Operating Conditions DDR 0 1 Pin Function Generic input port Generic output port Generic input port (but the DR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the DR bit) TPC pulse output 1 0 1 Sequential output of up to 16-bit patterns is possible by writing new output data to NDRA and NDRB before the next compare match. For information on non-overlapping operation, see section 9.3.4, Non-Overlapping TPC Output. 9.3.2 Output Timing If TPC output is enabled, NDRA/NDRB contents are transferred to PADR/PBDR and output when the selected compare match event occurs. Figure 9.3 shows the timing of these operations for the case of normal output in groups 0 and 1, triggered by compare match A. TCNT N N+1 GRA Compare match A signal N NDRA n PADR TP0 to TP7 m m n n Figure 9.3 Timing of Transfer of Next Data Register Contents and Output (Example) Rev.3.00 Mar. 26, 2007 Page 309 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.3.3 Normal TPC Output Sample Setup Procedure for Normal TPC Output Figure 9.4 shows a sample procedure for setting up normal TPC output. Normal TPC output Select GR functions Set GRA value ITU setup Select counting operation Select interrupt request 1 2 3 4 Set initial output data Select port output Port and TPC setup Enable TPC output Select TPC output trigger Set next TPC output data 5 6 7 8 9 Set TIOR to make GRA an output compare register (with output inhibited). 2. Set the TPC output trigger period. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TIER. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. Select the ITU compare match event to be used as the TPC output trigger in TPCR. 9. Set the next TPC output values in the NDR bits. 10. Set the STR bit to 1 in TSTR to start the timer counter. 11. At each IMFA interrupt, set the next output values in the NDR bits. 1. ITU setup Start counter 10 Compare match? Yes Set next TPC output data No 11 Figure 9.4 Setup Procedure for Normal TPC Output (Example) Rev.3.00 Mar. 26, 2007 Page 310 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Example of Normal TPC Output (Example of Five-Phase Pulse Output) Figure 9.5 shows an example in which the TPC is used for cyclic five-phase pulse output. TCNT value TCNT GRA Compare match H'0000 NDRA 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PADR 00 80 C0 40 60 20 30 10 18 08 88 80 C0 TP7 TP6 TP5 TP4 TP3 * * * * The ITU channel to be used as the output trigger channel is set up so that GRA is an output compare register and the counter will be cleared by compare match A. The trigger period is set in GRA. The IMIEA bit is set to 1 in TIER to enable the compare match A interrupt. H'F8 is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger. Output data H'80 is written in NDRA. The timer counter in this ITU channel is started. When compare match A occurs, the NDRA contents are transferred to PADR and output. The compare match/input capture A (IMFA) interrupt service routine writes the next output data (H'C0) in NDRA. Five-phase overlapping pulse output (one or two phases active at a time) can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive IMFA interrupts. Figure 9.5 Normal TPC Output Example (Five-Phase Pulse Output) Rev.3.00 Mar. 26, 2007 Page 311 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.3.4 Non-Overlapping TPC Output Sample Setup Procedure for Non-Overlapping TPC Output Figure 9.6 shows a sample procedure for setting up non-overlapping TPC output. Non-overlapping TPC output Select GR functions Set GR values ITU setup Select counting operation Select interrupt requests 3 4 1 2 1. Set TIOR to make GRA and GRB output compare registers (with output inhibited). 2. Set the TPC output trigger period in GRB and the non-overlap margin in GRA. 3. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. 4. Enable the IMFA interrupt in TIER. 5. Set the initial output values in the DR bits of the input/output port pins to be used for TPC output. 6. Set the DDR bits of the input/output port pins to be used for TPC output to 1. 7. Set the NDER bits of the pins to be used for TPC output to 1. 8. In TPCR, select the ITU compare match event to be used as the TPC output trigger. 9. In TPMR, select the groups that will operate in non-overlap mode. 10. Set the next TPC output values in the NDR bits. 11. Set the STR bit to 1 in TSTR to start the timer counter. 12. At each IMFA interrupt, write the next output value in the NDR bits. Set initial output data Set up TPC output Enable TPC transfer Port and TPC setup Select TPC transfer trigger Select non-overlapping groups Set next TPC output data 5 6 7 8 9 10 ITU setup Start counter 11 Compare match A? Yes Set next TPC output data No 12 Figure 9.6 Setup Procedure for Non-Overlapping TPC Output (Example) Rev.3.00 Mar. 26, 2007 Page 312 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Example of Non-Overlapping TPC Output (Example of Four-Phase Complementary Non-Overlapping Output) Figure 9.7 shows an example of the use of TPC output for four-phase complementary nonoverlapping pulse output. TCNT value GRB GRA H'0000 NDRA 95 65 59 56 95 65 Time TCNT PADR 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin TP7 TP6 TP5 TP4 TP3 TP2 TP1 TP0 * The ITU channel to be used as the output trigger channel is set up so that GRA and GRB are output compare registers and the counter will be cleared by compare match B. The TPC output trigger period is set in GRB. The non-overlap margin is set in GRA. The IMIEA bit is set to 1 in TIER to enable IMFA interrupts. * H'FF is written in PADDR and NDERA, and bits G1CMS1, G1CMS0, G0CMS1, and G0CMS0 are set in TPCR to select compare match in the ITU channel set up in step 1 as the output trigger. Bits G1NOV and G0NOV are set to 1 in TPMR to select non-overlapping output. Output data H'95 is written in NDRA. * The timer counter in this ITU channel is started. When compare match B occurs, outputs change from 1 to 0. When compare match A occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value of GRA). The IMFA interrupt service routine writes the next output data (H'65) in NDRA. * Four-phase complementary non-overlapping pulse output can be obtained by writing H'59, H'56, H'95... at successive IMFA interrupts. Figure 9.7 Non-Overlapping TPC Output Example (Four-Phase Complementary Non-Overlapping Pulse Output) Rev.3.00 Mar. 26, 2007 Page 313 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.3.5 TPC Output Triggering by Input Capture TPC output can be triggered by ITU input capture as well as by compare match. If GRA functions as an input capture register in the ITU channel selected in TPCR, TPC output will be triggered by the input capture signal. Figure 9.8 shows the timing. TIOC pin Input capture signal NDR N DR M N Figure 9.8 TPC Output Triggering by Input Capture (Example) Rev.3.00 Mar. 26, 2007 Page 314 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller 9.4 9.4.1 Usage Notes Operation of TPC Output Pins TP0 to TP15* are multiplexed with ITU pin functions. When ITU output is enabled, the corresponding pins cannot be used for TPC output. The data transfer from NDR bits to DR bits takes place, however, regardless of the usage of the pin. Pin functions should be changed only under conditions in which the output trigger event will not occur. Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output to the outside. 9.4.2 Note on Non-Overlapping Output During non-overlapping operation, the transfer of NDR bit values to DR bits takes place as follows. 1. NDR bits are always transferred to DR bits at compare match A. 2. At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 9.9 illustrates the non-overlapping TPC output operation. DDR Q NDER Q Compare match A Compare match B C Q TPC output pin DR D Q NDR D Figure 9.9 Non-Overlapping TPC Output Rev.3.00 Mar. 26, 2007 Page 315 of 682 REJ09B0353-0300 Section 9 Programmable Timing Pattern Controller Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the IMFA interrupt service routine write the next data in NDR, or by having the IMFA interrupt activate the DMAC. The next data must be written before the next compare match B occurs. Figure 9.10 shows the timing relationships. Compare match A Compare match B NDR write NDR write NDR DR 0 output 0/1 output Write to NDR in this interval Do not write to NDR in this interval Do not write to NDR in this interval 0 output 0/1 output Write to NDR in this interval Figure 9.10 Non-Overlapping Operation and NDR Write Timing Rev.3.00 Mar. 26, 2007 Page 316 of 682 REJ09B0353-0300 Section 10 Watchdog Timer Section 10 Watchdog Timer 10.1 Overview The H8/3039 Group has an on-chip watchdog timer (WDT). The WDT has two selectable functions: it can operate as a watchdog timer to supervise system operation, or it can operate as an interval timer. As a watchdog timer, it generates a reset signal for the H8/3039 Group chip if a system crash allows the timer counter (TCNT) to overflow before being rewritten. In interval timer operation, an interval timer interrupt is requested at each TCNT overflow. 10.1.1 Features WDT features are listed below. * Selection of eight counter clock sources /2, /32, /64, /128, /256, /512, /2048, or /4096 * Interval timer option * Timer counter overflow generates a reset signal or interrupt. The reset signal is generated in watchdog timer operation. An interval timer interrupt is generated in interval timer operation. * Watchdog timer reset signal resets the entire H8/3039 Group chip internally, and can also be output externally.* The reset signal generated by timer counter overflow during watchdog timer operation resets the entire H8/3039 Group internally. An external reset signal can be output from the RESO pin to reset other system devices simultaneously. Note: * The RESO pin of the mask ROM version is the dedicated FWE input pin of the FZTAT version. Therefore, the F-ZTAT version cannot output the reset signal to the outside. Rev.3.00 Mar. 26, 2007 Page 317 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.1.2 Block Diagram Figure 10.1 shows a block diagram of the WDT. Overflow TCNT Interrupt signal (interval timer) Interrupt control TCSR Read/ write control Internal data bus RSTCSR Internal clock sources /2 /32 /64 Clock Clock selector /128 /256 /512 /2048 /4096 Reset (internal, external) Reset control Legend: TCNT: Timer counter TCSR: Timer control/status register RSTCSR: Reset control/status register Figure 10.1 WDT Block Diagram 10.1.3 Pin Configuration Table 10.1 describes the WDT output pin.* Note: * Shows the mask ROM version pin. The F-ZTAT does not have any pins used by the WDT. For F-ZTAT version, see section 15.9, Notes on Flash Memory Programming/Erasing. Table 10.1 WDT Pin Name Reset output Note: * Abbreviation RESO I/O Output* Function External output of the watchdog timer reset signal Open-drain output. Externally pull-up to Vcc whether or not the reset output is used Rev.3.00 Mar. 26, 2007 Page 318 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.1.4 Register Configuration Table 10.2 summarizes the WDT registers. Table 10.2 WDT Registers Address* Write* 2 1 Read H'FFA8 H'FFA9 Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W R/(W)* R/W R/(W)* 3 3 Initial Value H'18 H'00 H'3F H'FFA8 H'FFAA H'FFAB Notes: 1. Lower 16 bits of the address. 2. Write word data starting at this address. 3. Only 0 can be written in bit 7 to clear the flag. 10.2 10.2.1 Register Descriptions Timer Counter (TCNT) TCNT is an 8-bit readable and writable* up-counter. Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from an internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), the OVF bit is set to 1 in TCSR. TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0. Note: * TCNT is write-protected by a password. For details see section 10.2.4, Notes on Register Access. Rev.3.00 Mar. 26, 2007 Page 319 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.2.2 Timer Control/Status Register (TCSR) TCSR is an 8-bit readable and writable* register. Its functions include selecting the timer mode and clock source. Note: * TCSR is write-protected by a password. For details see section 10.2.4, Notes on Register Access. Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select These bits select the TCNT clock source Reserved bits Timer enable Selects whether TCNT runs or halts Timer mode select Selects the mode Overflow flag Status flag indicating overflow Note: * Only 0 can be written to clear the flag. Bits 7 to 5 are initialized to 0 by a reset and in standby mode. Bits 2 to 0 are initialized to 0 by a reset. In software standby mode bits 2 to 0 are not initialized, but retain their previous values. Rev.3.00 Mar. 26, 2007 Page 320 of 682 REJ09B0353-0300 Section 10 Watchdog Timer Bit 7--Overflow Flag (OVF): This status flag indicates that the timer counter has overflowed from H'FF to H'00. Bit 7 OVF 0 Description [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 in OVF 1 [Setting condition] Set when TCNT changes from H'FF to H'00 (Initial value) Bit 6--Timer Mode Select (WT/IT Selects whether to use the WDT as a watchdog timer or IT): IT interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request when TCNT overflows. If used as a watchdog timer, the WDT generates a reset signal when TCNT overflows. Bit 6 WT/IT IT 0 1 Description Interval timer: requests interval timer interrupts Watchdog timer: generates a reset signal (Initial value) Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT is counting (Initial value) Bits 4 and 3--Reserved: These bits cannot be modified and are always read as 1. Bits 2 to 0--Clock Select 2 to 0 (CKS2/1/0): These bits select one of eight internal clock sources, obtained by prescaling the system clock (), for input to TCNT. Rev.3.00 Mar. 26, 2007 Page 321 of 682 REJ09B0353-0300 Section 10 Watchdog Timer Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description /2 /32 /64 /128 /256 /512 /2048 /4096 (Initial value) 10.2.3 Reset Control/Status Register (RSTCSR) RSTCSR is an 8-bit readable and writable* register that indicates when a reset signal has been generated by watchdog timer overflow, and controls external output of the reset signal. Note: * RSTCSR is write-protected by a password. For details see section 10.2.4, Notes on Register Access. Bit Initial value Read/Write 7 WRST 0 R/(W)*1 6 RSTOE 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Reserved bits Reset output enable*2 Enables or disables external output of the reset signal Watchdog timer reset Indicates that a reset signal has been generated Notes: 1. Only 0 can be written in bit 7 to clear the flag. 2. With the mask ROM version, enable and disable can be set. With the F-ZTAT version, do not set enable. Bits 7 and 6 are initialized by input of a reset signal at the RES pin. They are not initialized by reset signals generated by watchdog timer overflow. Rev.3.00 Mar. 26, 2007 Page 322 of 682 REJ09B0353-0300 Section 10 Watchdog Timer Bit 7--Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that TCNT has overflowed and generated a reset signal. This reset signal resets the entire chip 1 internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin* to initialize external system devices. Bit 7 WRST 0 Description [Clearing conditions] (1) Cleared to 0 by reset signal input at RES pin (2) Cleared by reading WRST when WRST = 1, then writing 0 in WERST 1 [Setting condition] Set when TCNT overflow generates a reset signal during watchdog timer operation (Initial value) Bit 6--Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin* of the reset signal generated if TCNT overflows during watchdog timer operation. 1 Bit 6 RSTOE 0 1 Description Reset signal is not output externally Reset signal is output externally* 2 (Initial value) Notes: 1. Mask ROM version. Dedicated FWE input pin for F-ZTAT version. 2. Mask ROM version. Do not set to 1 with the F-ZTAT version. Bits 5 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 323 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write. The procedures for writing and reading these registers are given below. Writing to TCNT and TCSR These registers must be written by a word transfer instruction. They cannot be written by byte instructions. Figure 10.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. The write data must be contained in the lower byte of the written word. The upper byte must contain H'5A (password for TCNT) or H'A5 (password for TCSR). This transfers the write data from the lower byte to TCNT or TCSR. 15 H'FFA8* H'5A 87 Write data 0 TCNT write Address TCSR write Address H'FFA8* 15 H'A5 87 Write data 0 Note: * Lower 16 bits of the address. Figure 10.2 Format of Data Written to TCNT and TCSR Rev.3.00 Mar. 26, 2007 Page 324 of 682 REJ09B0353-0300 Section 10 Watchdog Timer Writing to RSTCSR RSTCSR must be written by a word transfer instruction. It cannot be written by byte transfer instructions. Figure 10.3 shows the format of data written to RSTCSR. To write 0 in the WRST bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. The H'00 in the lower byte clears the WRST bit in RSTCSR to 0. To write to the RSTOE bit, the upper byte must contain H'5A and the lower byte must contain the write data. Writing this word transfers a write data value into the RSTOE bit. 15 H'A5 87 H'00 0 Writing 0 in WRST bit Address H'FFAA* Writing to RSTOE bit Address H'FFAA* 15 H'5A 87 Write data 0 Note: * Lower 16 bits of the address. Figure 10.3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR These registers are read like other registers. Byte access instructions can be used. The read addresses are H'FFA8 for TCSR, H'FFA9 for TCNT, and H'FFAB for RSTCSR, as listed in table 10.3. Table 10.3 Read Addresses of TCNT, TCSR, and RSTCSR Address* H'FFA8 H'FFA9 H'FFAB Note: * Register TCSR TCNT RSTCSR Lower 16 bits of the address. Rev.3.00 Mar. 26, 2007 Page 325 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.3 Operation Operations when the WDT is used as a watchdog timer and as an interval timer are described below. 10.3.1 Watchdog Timer Operation Figure 10.4 illustrates watchdog timer operation. To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1 in TCSR. Software must prevent TCNT overflow by rewriting the TCNT value (normally by writing H'00) before overflow occurs. If TCNT fails to be rewritten and overflows due to a system crash etc., the H8/3039 Group is internally reset for a duration of 518 states. The watchdog reset signal can be externally output from the RESO pin* to reset external system devices. The reset signal is output externally for 132 states. External output can be enabled or disabled by the RSTOE bit in RSTCSR. A watchdog reset has the same vector as a reset generated by input at the RES pin. Software can distinguish a RES reset from a watchdog reset by checking the WRST bit in RSTCSR. If a RES reset and a watchdog reset occur simultaneously, the RES reset takes priority. Note: * Mask ROM version. Since the RES pin is a dedicated FWE input pin with the F-ZTAT version, the reset signal cannot be output to the outside. Rev.3.00 Mar. 26, 2007 Page 326 of 682 REJ09B0353-0300 Section 10 Watchdog Timer H'FF TCNT count value H'00 WDT overflow TME set to 1 OVF = 1 Start Internal reset signal H'00 written in TCNT Reset H'00 written in TCNT 518 states RESO 132 states Figure 10.4 Watchdog Timer Operation (Mask ROM Version) 10.3.2 Interval Timer Operation Figure 10.5 illustrates interval timer operation. To use the WDT as an interval timer, clear bit WT/IT to 0 and set bit TME to 1 in TCSR. An interval timer interrupt request is generated at each TCNT overflow. This function can be used to generate interval timer interrupts at regular intervals. H'FF TCNT count value Time t H'00 WT/ IT = 0 TME = 1 Interval timer interrupt Interval timer interrupt Interval timer interrupt Interval timer interrupt Interval timer interrupt Figure 10.5 Interval Timer Operation Rev.3.00 Mar. 26, 2007 Page 327 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.3.3 Timing of Setting of Overflow Flag (OVF) Figure 10.6 shows the timing of setting of the OVF flag in TCSR. The OVF flag is set to 1 when TCNT overflows. At the same time, a reset signal is generated in watchdog timer operation, or an interval timer interrupt is generated in interval timer operation. TCNT H'FF H'00 Overflow signal OVF Figure 10.6 Timing of Setting of OVF Rev.3.00 Mar. 26, 2007 Page 328 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) The WRST bit in RSTCSR is valid when bits WT/IT and TME are both set to 1 in TCSR. Figure 10.7 shows the timing of setting of WRST and the internal reset timing. The WRST bit is set to 1 when TCNT overflows and OVF is set to 1. At the same time an internal reset signal is generated for the entire H8/3039 Group chip. This internal reset signal clears OVF to 0, but the WRST bit remains set to 1. The reset routine must therefore clear the WRST bit. TCNT H'FF H'00 Overflow signal OVF WDT internal reset WRST Figure 10.7 Timing of Setting of WRST Bit and Internal Reset 10.4 Interrupts During interval timer operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF bit is set to 1 in TCSR. Rev.3.00 Mar. 26, 2007 Page 329 of 682 REJ09B0353-0300 Section 10 Watchdog Timer 10.5 Usage Notes Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T3 state of a write cycle to TCNT, the write takes priority and the timer count is not incremented. See figure 10.8. Write cycle: CPU writes to TCNT T1 T2 T3 TCNT Internal write signal TCNT input clock TCNT N M Counter write data Figure 10.8 Contention between TCNT Write and Increment Changing CKS2 to CKS0 Values Halt TCNT by clearing the TME bit to 0 in TCSR before changing the values of bits CKS2 to CKS0. Rev.3.00 Mar. 26, 2007 Page 330 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Section 11 Serial Communication Interface 11.1 Overview The H8/3039 Group has a serial communication interface (SCI) with two independent channels. The two channels are functionally identical. The SCI can communicate in asynchronous or synchronous mode. It also has a multiprocessor communication function for serial communication among two or more processors. When the SCI is not used, it can be halted to conserve power. Each SCI channel can be halted independently. For details see section 17.6, Module Standby Function. Channel 0 (SCI0) also has a smart card interface function conforming to the ISO/IEC7816-3 (Identification Card) standard. This function supports serial communication with a smart card. For details, see section 12, Smart Card Interface. 11.1.1 Features SCI features are listed below. * Selection of asynchronous or synchronous mode for serial communication a. Asynchronous mode Serial data communication is synchronized one character at a time. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), asynchronous communication interface adapter (ACIA), or other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. Data length: Stop bit length: Parity bit: Multiprocessor bit: Break detection: 7 or 8 bits 1 or 2 bits even, odd, or none 1 or 0 by reading the RxD level directly when a framing error occurs Receive error detection: parity, overrun, and framing errors Rev.3.00 Mar. 26, 2007 Page 331 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface b. Synchronous mode Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a synchronous communication function. There is one serial data communication format. Data length: * Full-duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. The transmitting and receiving sections are both double-buffered, so serial data can be transmitted and received continuously. * Built-in baud rate generator with selectable bit rates * Selectable transmit/receive clock sources: internal clock from baud rate generator, or external clock from the SCK pin. * Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. 8 bits Receive error detection: overrun errors Rev.3.00 Mar. 26, 2007 Page 332 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the SCI. Bus interface BRR Baud rate generator Clock External clock TEI TXI RXI ERI Internal data bus Module data bus RDR RxD RSR TDR TSR SSR SCR SMR Transmit/ receive control TxD /4 /16 /64 Parity generation Parity check SCK Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 11.1 SCI Block Diagram Rev.3.00 Mar. 26, 2007 Page 333 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.1.3 Input/Output Pins The SCI has the serial pins for each channel as listed in table 11.1. Table 11.1 SCI Pins Channel 0 Name Serial clock pin Receive data pin Transmit data pin 1 Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O Input/output Input Output Input/output Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output Rev.3.00 Mar. 26, 2007 Page 334 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.1.4 Register Configuration The SCI has the internal registers as listed in table 11.2. These registers select asynchronous or synchronous mode, specify the data format and bit rate, and control the transmitter and receiver sections. Table 11.2 Registers Channel 0 Address* H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 1 H'FFB8 H'FFB9 H'FFBA H'FFBB H'FFBC H'FFBD 1 Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Abbreviation SMR BRR SCR TDR SSR RDR SMR BRR SCR TDR SSR RDR R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/(W)* R 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'00 H'FF H'00 H'FF H'84 H'00 Notes: 1. Lower 16 bits of the address. 2. Only 0 can be written to clear flags. Rev.3.00 Mar. 26, 2007 Page 335 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.2 11.2.1 Register Descriptions Receive Shift Register (RSR) RSR is an 8-bit register that receives serial data. Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- The SCI loads serial data input at the RxD pin into RSR in the order received, LSB (bit 0) first, thereby converting the data to parallel data. When 1 byte has been received, it is automatically transferred to RDR. The CPU cannot read or write RSR directly. 11.2.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received serial data. Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R When the SCI finishes receiving 1 byte of serial data, it transfers the received data from RSR into RDR for storage. RSR is then ready to receive the next data. This double buffering allows data to be received continuously. RDR is a read-only register. Its contents cannot be modified by the CPU. RDR is initialized to H'00 by a reset and in standby mode. Rev.3.00 Mar. 26, 2007 Page 336 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.2.3 Transmit Shift Register (TSR) TSR is an 8-bit register used to transmit serial data. Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- The SCI loads transmit data from TDR into TSR, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from TDR into TSR and starts transmitting it. If the TDRE flag is set to 1 in SSR, however, the SCI does not load the TDR contents into TSR. The CPU cannot read or write TSR directly. 11.2.4 Transmit Data Register (TDR) TDR is an 8-bit register that stores data for serial transmission. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W When the SCI detects that TSR is empty, it moves transmit data written in TDR from TDR into TSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in TDR during serial transmission from TSR. The CPU can always read and write TDR. TDR is initialized to H'FF by a reset and in standby mode. Rev.3.00 Mar. 26, 2007 Page 337 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.2.5 Serial Mode Register (SMR) SMR is an 8-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. Bit Initial value Read/Write 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Clock select 1/0 These bits select the baud rate generatorOs clock source Multiprocessor mode Selects the multiprocessor function Stop bit length Selects the stop bit length Parity mode Selects even or odd parity Parity enable Selects whether a parity bit is added Character length Selects character length in asynchronous mode Communication mode Selects asynchronous or synchronous mode The CPU can always read and write SMR. SMR is initialized to H'00 by a reset and in standby mode. Bit 7--Communication Mode (C/A): Selects whether the SCI operates in asynchronous or A synchronous mode. Bit 7 C/A A 0 1 Description Asynchronous mode Synchronous mode (Initial value) Rev.3.00 Mar. 26, 2007 Page 338 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 6--Character Length (CHR): Selects 7-bit or 8-bit data length in asynchronous mode. In synchronous mode the data length is 8 bits regardless of the CHR setting. Bit 6 CHR 0 1 Note: * Description 8-bit data 7-bit data* When 7-bit data is selected, the MSB (bit 7) in TDR is not transmitted. (Initial value) Bit 5--Parity Enable (PE): In asynchronous mode, this bit enables or disables the addition of a parity bit to transmit data, and the checking of the parity bit in receive data. In synchronous mode the parity bit is neither added nor checked, regardless of the PE setting. Bit 5 PE 0 1 Note: * Description Parity bit not added or checked Parity bit added and checked* When PE is set to 1, an even or odd parity bit is added to transmit data according to the even or odd parity mode selected by the O/E bit, and the parity bit in receive data is checked to see that it matches the even or odd mode selected by the O/E bit. (Initial value) Bit 4--Parity Mode (O/E): Selects even or odd parity. The O/E bit setting is valid in E asynchronous mode when the PE bit is set to 1 to enable the adding and checking of a parity bit. The O/E setting is ignored in synchronous mode, or when parity adding and checking is disabled in asynchronous mode. Bit 4 O/E E 0 1 Description Even parity* Odd parity* 2 1 (Initial value) Notes: 1. When even parity is selected, the parity bit added to transmit data makes an even number of 1s in the transmitted character and parity bit combined. Receive data must have an even number of 1s in the received character and parity bit combined. 2. When odd parity is selected, the parity bit added to transmit data makes an odd number of 1s in the transmitted character and parity bit combined. Receive data must have an odd number of 1s in the received character and parity bit combined. Bit 3--Stop Bit Length (STOP): Selects one or two stop bits in asynchronous mode. This setting is used only in asynchronous mode. In synchronous mode no stop bit is added, so the STOP bit setting is ignored. Rev.3.00 Mar. 26, 2007 Page 339 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 3 STOP 0 1 Description One stop bit* 1 2 (Initial value) Two stop bits* Notes: 1. One stop bit (with value 1) is added at the end of each transmitted character. 2. Two stop bits (with value 1) are added at the end of each transmitted character. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1 it is treated as a stop bit. If the second stop bit is 0 it is treated as the start bit of the next incoming character. Bit 2--Multiprocessor Mode (MP): Selects a multiprocessor format. When a multiprocessor format is selected, parity settings made by the PE and O/E bits are ignored. The MP bit setting is valid only in asynchronous mode. It is ignored in synchronous mode. For further information on the multiprocessor communication function, see section 11.3.3, Multiprocessor Communication. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1/0): These bits select the clock source of the on-chip baud rate generator. Four clock sources are available: , /4, /16, and /64. For the relationship between the clock source, bit rate register setting, and baud rate, see section 11.2.8, Bit Rate Register (BRR). Bit 1 CKS1 0 0 1 1 Bit 0 CKS0 0 1 0 1 Description clock selected /4 clock selected /16 clock selected /64 clock selected (Initial value) Rev.3.00 Mar. 26, 2007 Page 340 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.2.6 Serial Control Register (SCR) SCR enables the SCI transmitter and receiver, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the transmit/receive clock source. Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Clock enable 1/0 These bits select the SCI clock source Transmit end interrupt enable Enables or disables transmitend interrupts (TEI) Multiprocessor interrupt enable Enables or disables multiprocessor interrupts Receive enable Enables or disables the receiver Transmit enable Enables or disables the transmitter Receive interrupt enable Enables or disables receive-data-full interrupts (RXI) and receive-error interrupts (ERI) Transmit interrupt enable Enables or disables transmit-data-empty interrupts (TXI) The CPU can always read and write SCR. SCR is initialized to H'00 by a reset and in standby mode. Rev.3.00 Mar. 26, 2007 Page 341 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 7--Transmit Interrupt Enable (TIE): Enables or disables the transmit-data-empty interrupt (TXI) requested when the TDRE flag in SSR is set to 1 due to transfer of serial transmit data from TDR to TSR. Bit 7 TIE 0 1 Note: * Description Transmit-data-empty interrupt request (TXI) is disabled* Transmit-data-empty interrupt request (TXI) is enabled TXI interrupt requests can be cleared by reading the value 1 from the TDRE flag, then clearing it to 0; or by clearing the TIE bit to 0. (Initial value) Bit 6--Receive Interrupt Enable (RIE): Enables or disables the receive-data-full interrupt (RXI) requested when the RDRF flag is set to 1 in SSR due to transfer of serial receive data from RSR to RDR; also enables or disables the receive-error interrupt (ERI). Bit 6 RIE 0 1 Note: * Description Receive-end (RXI) and receive-error (ERI) interrupt requests are disabled* (Initial value) Receive-end (RXI) and receive-error (ERI) interrupt requests are enabled RXI and ERI interrupt requests can be cleared by reading the value 1 from the RDRF, FER, PER, or ORER flag, then clearing it to 0; or by clearing the RIE bit to 0. Bit 5--Transmit Enable (TE): Enables or disables the start of SCI serial transmitting operations. Bit 5 TE 0 1 Description Transmitting disabled* Transmitting enabled* 1 (Initial value) 2 Notes: 1. The TDRE flag is fixed at 1 in SSR. 2. In the enabled state, serial transmitting starts when the TDRE flag in SSR is cleared to 0 after writing of transmit data into TDR. Select the transmit format in SMR before setting the TE bit to 1. Rev.3.00 Mar. 26, 2007 Page 342 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 4--Receive Enable (RE): Enables or disables the start of SCI serial receiving operations. Bit 4 RE 0 1 Description Receiving disabled* Receiving enabled* 1 (Initial value) 2 Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags. These flags retain their previous values. 2. In the enabled state, serial receiving starts when a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Select the receive format in SMR before setting the RE bit to 1. Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE setting is valid only in asynchronous mode, and only if the MP bit is set to 1 in SMR. The MPIE setting is ignored in synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts are disabled (normal receive operation) [Clearing conditions] * * 1 The MPIE bit is cleared to 0 MPB = 1 in received data (Initial value) Multiprocessor interrupts are enabled* Receive-data-full interrupts (RXI), receive-error interrupts (ERI), and setting of the RDRF, FER, and ORER status flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * The SCI does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in SSR. When it receives data in which MPB = 1, the SCI sets the MPB bit to 1 in SSR, automatically clears the MPIE bit to 0, and enables RXI and ERI interrupts (if the RIE bit is set to 1 in SCR) and setting of the FER and ORER flags. Rev.3.00 Mar. 26, 2007 Page 343 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 2--Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt (TEI) requested if TDR does not contain new transmit data when the MSB is transmitted. Bit 2 TEIE 0 1 Note: * Description Transmit-end interrupt requests (TEI) are disabled* Transmit-end interrupt requests (TEI) are enabled* TEI interrupt requests can be cleared by reading the value 1 from the TDRE flag in SSR, then clearing the TDRE flag to 0, thereby also clearing the TEND flag to 0; or by clearing the TEIE bit to 0. (Initial value) Bits 1 and 0--Clock Enable 1 and 0 (CKE1/0): These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the settings of CKE1 and CKE0, the SCK pin can be used for generic input/output, serial clock output, or serial clock input. The CKE0 setting is valid only in asynchronous mode, and only when the SCI is internally clocked (CKE1 = 0). The CKE0 setting is ignored in synchronous mode, or when an external clock source is selected (CKE1 = 1). After setting the CKE1 and CKE0 bits, select the SCI operating mode in SMR. For further details on selection of the SCI clock source, see table 11.9. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Synchronous mode 0 1 Asynchronous mode Synchronous mode 1 0 Asynchronous mode Synchronous mode 1 1 Asynchronous mode Synchronous mode Internal clock, SCK pin available for generic 1 input/output* Internal clock, SCK pin used for serial clock output* Internal clock, SCK pin used for clock output* 2 1 Internal clock, SCK pin used for serial clock output External clock, SCK pin used for clock input* 3 External clock, SCK pin used for serial clock input External clock, SCK pin used for clock input* 3 External clock, SCK pin used for serial clock input Notes: 1. Initial value 2. The output clock frequency is the same as the bit rate. 3. The input clock frequency is 16 times the bit rate. Rev.3.00 Mar. 26, 2007 Page 344 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.2.7 Serial Status Register (SSR) SSR is an 8-bit register containing multiprocessor bit values, and status flags that indicate the SCI operating status. Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor bit transfer Value of multiprocessor bit to be transmitted Multiprocessor bit Stores the received multiprocessor bit value Transmit end Status flag indicating end of transmission Parity error Status flag indicating detection of a receive parity error Framing error Status flag indicating detection of a receive framing error Overrun error Status flag indicating detection of a receive overrun error Receive data register full Status flag indicating that data has been received and stored in RDR Transmit data register empty Status flag indicating that transmit data has been transferred from TDR into TSR and new data can be written in TDR Note: * Only 0 can be written to clear the flag. The CPU can always read and write SSR, but cannot write 1 in the TDRE, RDRF, ORER, PER, and FER flags. These flags can be cleared to 0 only if they have first been read while set to 1. The TEND and MPB flags are read-only bits that cannot be written. Rev.3.00 Mar. 26, 2007 Page 345 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface SSR is initialized to H'84 by a reset and in standby mode. Bit 7--Transmit Data Register Empty (TDRE): Indicates that the SCI has loaded transmit data from TDR into TSR and the next serial transmit data can be written in TDR. Bit 7 TDRE 0 Description TDR contains valid transmit data [Clearing condition] Software reads TDRE while it is set to 1, then writes 0 1 TDR does not contain valid transmit data [Setting conditions] * * * The chip is reset or enters standby mode The TE bit in SCR is cleared to 0 TDR contents are loaded into TSR, so new data can be written in TDR (Initial value) Bit 6--Receive Data Register Full (RDRF): Indicates that RDR contains new receive data. Bit 6 RDRF 0 Description RDR does not contain new receive data [Clearing conditions] * * * 1 The chip is reset or enters standby mode Software reads RDRF while it is set to 1, then writes 0 The DMAC reads data from RDR (Initial value) RDR contains new receive data [Setting condition] When serial data is received normally and transferred from RSR to RDR Note: The RDR contents and RDRF flag are not affected by detection of receive errors or by clearing of the RE bit to 0 in SCR. They retain their previous values. If the RDRF flag is still set to 1 when reception of the next data ends, an overrun error occurs and receive data is lost. Rev.3.00 Mar. 26, 2007 Page 346 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 5--Overrun Error (ORER): Indicates that data reception ended abnormally due to an overrun error. Bit 5 ORER 0 Description Receiving is in progress or has ended normally [Clearing conditions] * * 1 The chip is reset or enters standby mode Software reads ORER while it is set to 1, then writes 0 2 (Initial value)* 1 A receive overrun error occurred* [Setting condition] Reception of the next serial data ends when RDRF = 1 Notes: 1. Clearing the RE bit to 0 in SCR does not affect the ORER flag, which retains its previous value. 2. RDR continues to hold the receive data before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while the ORER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Bit 4--Framing Error (FER): Indicates that data reception ended abnormally due to a framing error in asynchronous mode. Bit 4 FER 0 Description Receiving is in progress or has ended normally [Clearing conditions] * * 1 The chip is reset or enters standby mode Software reads FER while it is set to 1, then writes 0 2 (Initial value)* 1 A receive framing error occurred* [Setting condition] The stop bit at the end of receive data is checked and found to be 0 Notes: 1. Clearing the RE bit to 0 in SCR does not affect the FER flag, which retains its previous value. 2. When the stop bit length is 2 bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the FER flag is set to 1. In synchronous mode, serial transmitting is also disabled. Rev.3.00 Mar. 26, 2007 Page 347 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 3--Parity Error (PER): Indicates that data reception ended abnormally due to a parity error in asynchronous mode. Bit 3 PER 0 Description Receiving is in progress or has ended normally* [Clearing condition] The chip is reset or enters standby mode. Software reads PER while it is set to 1, then writes 0 1 A receive parity error occurred* [Setting condition] The number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of O/E in SMR Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous value. 2. When a parity error occurs the SCI transfers the receive data into RDR but does not set the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In synchronous mode, serial transmitting is also disabled. 2 1 (Initial value) Bit 2--Transmit End (TEND): Indicates that when the last bit of a serial character was transmitted TDR did not contain new transmit data, so transmission has ended. The TEND flag is a read-only bit and cannot be written. Bit 2 TEND 0 Description Transmission is in progress [Clearing condition] Software reads TDRE while it is set to 1, then writes 0 in the TDRE flag 1 End of transmission [Setting conditions] * * The chip is reset or enters standby mode. The TE bit is cleared to 0 in SCR TDRE is 1 when the last bit of a serial character is transmitted (Initial value) Rev.3.00 Mar. 26, 2007 Page 348 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Bit 1--Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in receive data when a multiprocessor format is used in asynchronous mode. MPB is a read-only bit and cannot be written. Bit 1 MPB 0 1 Note: * Description Multiprocessor bit value in receive data is 0* Multiprocessor bit value in receive data is 1 If the RE bit is cleared to 0 when a multiprocessor format is selected, MPB retains its previous value. (Initial value) Bit 0--Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in asynchronous mode. The MPBT setting is ignored in synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. Bit 0 MPBT 0 1 Description Multiprocessor bit value in transmit data is 0 Multiprocessor bit value in transmit data is 1 (Initial value) 11.2.8 Bit Rate Register (BRR) BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR that select the baud rate generator clock source, determines the serial communication bit rate. Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W The CPU can always read and write BRR. BRR is initialized to H'FF by a reset and in standby mode. The baud rate generator is controlled separately for the individual channels, so different values may be set for each. Table 11.3 shows examples of BRR settings in asynchronous mode. Table 11.4 shows examples of BRR settings in synchronous mode. Rev.3.00 Mar. 26, 2007 Page 349 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Table 11.3 Examples of Bit Rates and BRR Settings in Asynchronous Mode (MHz) 2 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 8.51 0 -18.62 n 1 1 0 0 0 0 0 0 0 0 0 2.097152 N 148 108 217 108 54 26 13 6 2 1 1 Error (%) -0.04 0.21 0.21 0.21 -0.70 1.14 -2.48 -2.48 13.78 4.86 -14.67 n 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 63 31 15 7 3 1 1 2.4576 Error (%) -0.26 0 0 0 0 0 0 0 0 22.88 0 n 1 1 1 0 0 0 0 0 0 0 N 212 155 77 155 77 38 19 9 4 2 3 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0 -- ---- (MHz) 3.6864 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 47 23 11 5 Error (%) 0.70 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 4 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -6.99 0 8.51 n 2 1 1 0 0 0 0 0 0 0 0 4.9152 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) 0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 5 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0 1.73 ---- 0 2 Rev.3.00 Mar. 26, 2007 Page 350 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface (MHz) 6 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 0 -2.34 n 2 2 1 1 0 0 0 0 0 0 0 N 108 79 159 79 159 79 39 19 9 5 4 6.144 Error (%) 0.08 0 0 0 0 0 0 0 0 2.40 0 n 2 2 1 1 0 0 0 0 0 0 0 (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0 -2.34 n 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 12.288 Error (%) 0.08 0 0 0 0 0 0 0 0 2.40 0 7.3728 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0 0 0 0 0 0 0 0 5.33 0 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 -6.99 Rev.3.00 Mar. 26, 2007 Page 351 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface (MHz) 14 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 11 10 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0 3.57 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 14.7456 Error (%) 0.70 0 0 0 0 0 0 0 0 -1.70 0 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0 0.16 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 Rev.3.00 Mar. 26, 2007 Page 352 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Table 11.4 Examples of Bit Rates and BRR Settings in Synchronous Mode (MHz) Bit Rate (bits/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2M 2.5 M 4M Legend: Blank: No setting available --: Setting possible, but error occurs *: Continuous transmission/reception not possible Note: Settings with an error of 1% or less are recommended. 2 n 3 2 1 1 0 0 0 0 0 0 0 0 N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 4 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- 3 2 2 1 1 0 0 0 0 0 0 0 0 -- 8 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* -- n -- -- -- -- 1 1 0 0 0 0 0 0 -- -- 0 10 N -- -- -- -- 249 124 249 99 49 24 9 4 -- -- 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 -- 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 -- 0* n -- -- 3 3 2 1 1 0 0 0 0 0 0 -- -- -- 18 N -- -- 140 69 112 224 112 179 89 44 17 8 4 -- -- -- Rev.3.00 Mar. 26, 2007 Page 353 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface The BRR setting is calculated as follows: Asynchronous mode: N= 64 x 2 2n-1 xB x 10 - 1 6 Synchronous mode: N= 8x2 2n-1 xB x 10 - 1 6 B: N: : n: Bit rate (bits/s) BRR setting for baud rate generator (0 N 255) System clock frequency (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (For the clock sources and values of n, see the following table.) SMR Settings n 0 1 2 3 Clock Source /4 /16 /64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is calculated as follows. Error (%) = { x10 6 2n-1 (N + 1) x B x 64 x 2 - 1} x 100 Rev.3.00 Mar. 26, 2007 Page 354 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Table 11.5 indicates the maximum bit rates in asynchronous mode for various system clock frequencies. Tables 11.6 and 11.7 indicate the maximum bit rates with external clock input. Table 11.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Settings (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 Maximum Bit Rate (bits/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Rev.3.00 Mar. 26, 2007 Page 355 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Table 11.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 Maximum Bit Rate (bits/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 Rev.3.00 Mar. 26, 2007 Page 356 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Table 11.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) (MHz) 2 4 6 8 10 12 14 16 18 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 Maximum Bit Rate (bits/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 Rev.3.00 Mar. 26, 2007 Page 357 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.3 11.3.1 Operation Overview The SCI has an asynchronous mode in which characters are synchronized individually, and a synchronous mode in which communication is synchronized with clock pulses. Serial communication is possible in either mode. Asynchronous or synchronous mode and the communication format are selected in SMR, as shown in table 11.8. The SCI clock source is selected by the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 11.9. Asynchronous Mode: * Data length is selectable: 7 or 8 bits. * Parity and multiprocessor bits are selectable, and so is the stop bit length (1 or 2 bits). These selections determine the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors, overrun errors, and the break state. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Synchronous Mode: * The communication format has a fixed 8-bit data length. * In receiving, it is possible to detect overrun errors. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates using the on-chip baud rate generator, and outputs a serial clock signal to external devices. When an external clock is selected, the SCI operates on the input serial clock. The on-chip baud rate generator is not used. Rev.3.00 Mar. 26, 2007 Page 358 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Table 11.8 SMR Settings and Serial Communication Formats SMR Settings Bit 7 C/A A 0 0 0 0 0 0 0 0 0 0 0 0 1 Bit 6 CHR 0 0 0 0 1 1 1 1 0 0 1 1 -- Bit 2 MP 0 0 0 0 0 0 0 0 1 1 1 1 -- Bit 5 PE 0 0 1 1 0 0 1 1 -- -- -- -- -- Bit 3 STOP 0 1 0 1 0 1 0 1 0 1 0 1 -- Synchronous mode 8-bit data Absent Asynchronous mode (mult i processor format) 8-bit data Present Absent Present 7-bit data Absent SCI Communication Format Data Length 8-bit data Multiprocessor Parity Bit Bit Absent Absent Stop Bit Length 1 bit 2 bits Present 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Mode Asynchronous mode Table 11.9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A A 0 0 0 0 1 1 1 1 SCR Settings Bit 1 CKE1 0 0 1 1 0 0 1 1 Bit 0 CKE0 0 1 0 1 0 1 0 1 Synchronous mode Internal SCI Communication Format Mode Asynchronous mode Clock Source Internal SCK Pin Function SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate External Inputs a clock with frequency 16 times the bit rate Outputs the serial clock External Inputs the serial clock Rev.3.00 Mar. 26, 2007 Page 359 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.3.2 Operation in Asynchronous Mode In asynchronous mode each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full-duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 11.2 shows the general format of asynchronous serial communication. In asynchronous serial communication the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in asynchronous mode, the SCI synchronizes at the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idle (mark) state 1 0/1 Parity bit 1 Stop bit 1 1 Serial data 0 Start bit 1 bit (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 Transmit or receive data 7 bits or 8 bits One unit of data (character or frame) 1 bit or 1 bit or no bit 2 bits Figure 11.2 Data Format in Asynchronous Communication (Example: 8-Bit Data with Parity and 2 Stop Bits) Rev.3.00 Mar. 26, 2007 Page 360 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Communication Formats Table 11.10 shows the 12 communication formats that can be selected in asynchronous mode. The format is selected by settings in SMR. Table 11.10 Serial Communication Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S Serial Communication Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB STOP STOP STOP STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8 bit data S S S 8 bit data 7-bit data 7-bit data MPB STOP STOP MPB STOP MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Rev.3.00 Mar. 26, 2007 Page 361 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SMR and bits CKE1 and CKE0 in SCR. See table 11.9. When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal at the SCK pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 11.3 so that the rising edge of the clock occurs at the center of each transmit data bit. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 11.3 Phase Relationship between Output Clock and Serial Data (Asynchronous Mode) Transmitting and Receiving Data SCI Initialization (Asynchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets the TDRE flag to 1 and initializes TSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and RDR, which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 11.4 shows a sample flowchart for initializing the SCI. Rev.3.00 Mar. 26, 2007 Page 362 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) 1 1. Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made in SCR. 2. Select the communication format in SMR. 3. Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. 4. Wait for at least the interval required to transmit or receive 1 bit, then set the TE or RE bit to 1 in SCR. Set the RIE, TIE, TEIE, and MPIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. Select communication format in SMR 2 Set value in BRR Wait 3 1 bit interval elapsed? Yes Set TE or RE bit to 1 in SCR Set RIE, TIE, TEIE, and MPIE bits as necessary No 4 Transmitting or receiving Figure 11.4 Sample Flowchart for SCI Initialization Rev.3.00 Mar. 26, 2007 Page 363 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Transmitting Serial Data (Asynchronous Mode): Figure 11.5 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear the TE bit to 0 in SCR. Initialize Start transmitting Read TDRE flag in SSR 2 No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted? Yes No 3 Read TEND flag in SSR No TEND = 1? Yes Output break signal? Yes Clear DR bit to 0, set DDR bit to 1 Clear TE bit to 0 in SCR No 4 End Figure 11.5 Sample Flowchart for Transmitting Serial Data Rev.3.00 Mar. 26, 2007 Page 364 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface In transmitting serial data, the SCI operates as follows. * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: Transmit data: One 0 bit is output. 7 or 8 bits are output, LSB first. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. Stop bit: Mark state: One or two 1 bits (stop bits) are output. Output of 1 continues until the start bit of the next transmit data. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads new data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, outputs the stop bit, then continues output of 1 in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time. Figure 11.6 shows an example of SCI transmit operation in asynchronous mode. Start bit 0 1 Data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 Data D0 D1 D7 Parity Stop bit bit 0/1 1 1 Idle (mark) state TDRE TEND TXI interrupt request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 1 frame TXI interrupt request TEI interrupt request Figure 11.6 Example of SCI Transmit Operation in Asynchronous Mode (8-Bit Data with Parity and 1 Stop Bit) Rev.3.00 Mar. 26, 2007 Page 365 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Receiving Serial Data (Asynchronous Mode): Figure 11.7 shows a sample flowchart for receiving serial data and indicates the procedure to follow. Initialize 1 Start receiving Read ORER, PER, and FER flags in SSR 2 PER FER ORER = 1? No Yes 3 Error handling (continued on next page) Read RDRF flag in SSR 4 No RDRF = 1? Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR 1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3. Receive error handling and break detection: if a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER, PER, and FER flags all to 0. Receiving cannot resume if any of the ORER, PER, and FER flags remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. 4. SCI status check and receive data read: read SSR, check that RDRF is set to 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. 5. To continue receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the stop bit of the current frame is received. No Finished receiving? Yes Clear RE bit to 0 in SCR End 5 Figure 11.7 Sample Flowchart for Receiving Serial Data (1) Rev.3.00 Mar. 26, 2007 Page 366 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 3 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags to 0 in SSR End Figure 11.7 Sample Flowchart for Receiving Serial Data (2) Rev.3.00 Mar. 26, 2007 Page 367 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface In receiving, the SCI operates as follows. * The SCI monitors the receive data line. When it detects a start bit, the SCI synchronizes internally and starts receiving. * Receive data is stored in RSR in order from LSB to MSB. * The parity bit and stop bit are received. After receiving data, the SCI makes the following checks: Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in SMR. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. Status check: The RDRF flag must be 0 so that receive data can be transferred from RSR into RDR. If these checks all pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one of the checks fails (receive error)*, the SCI operates as indicated in table 11.11. Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag is not set to 1. Be sure to clear the error flags. * When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt (RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also set to 1, a receive-error interrupt (ERI) is requested. Table 11.11 Receive Error Conditions Receive Error Overrun error Abbreviation ORER Condition Data Transfer Receiving of next data ends Receive data not transferred while RDRF flag is still set to 1 from RSR to RDR in SSR Stop bit is 0 Parity of receive data differs from even/odd parity setting in SMR Receive data transferred from RSR to RDR Receive data transferred from RSR to RDR Framing error Parity error FER PER Rev.3.00 Mar. 26, 2007 Page 368 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Figure 11.8 shows an example of SCI receive operation in asynchronous mode. Start bit 0 1 Data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 Data D0 D1 D7 Parity Stop bit bit 0/1 1 1 Idle (mark) state RDRF FER RXI request 1 frame RXI interrupt handler reads data in RDR and clears RDRF flag to 0 Framing error, ERI request Figure 11.8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit) 11.3.3 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 11.9 shows an example of communication among different processors using a multiprocessor format. Rev.3.00 Mar. 26, 2007 Page 369 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Communication Formats Four formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 11.11. Clock See the description of asynchronous mode. Transmitting processor Serial communication line Receiving processor A (ID = 01) Receiving processor B Receiving processor C Receiving processor D (ID = 02) (ID = 03) (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle: receiving processor address H'AA (MPB = 0) Data-sending cycle: data sent to receiving processor specified by ID Legend: MPB: Multiprocessor bit Figure 11.9 Example of Communication among Processors using Multiprocessor Format (Sending Data H'AA to Receiving Processor A) Rev.3.00 Mar. 26, 2007 Page 370 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Transmitting and Receiving Data Transmitting Multiprocessor Serial Data: Figure 11.10 shows a sample flowchart for transmitting multiprocessor serial data and indicates the procedure to follow. Initialize Start transmitting 1 Read TDRE flag in SSR TDRE = 1? Yes Write transmit data in TDR and set MPBT bit in SSR Clear TDRE flag to 0 No No 2 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR. Also set the MPBT flag to 0 or 1 in SSR. Finally, clear the TDRE flag to 0. 3. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. 4. To output a break signal at the end of serial transmission: set the DDR bit to 1 and clear the DR bit to 0 (DDR and DR are I/O port registers), then clear the TE bit to 0 in SCR. All data transmitted? Yes Read TEND flag in SSR 3 TEND = 1? Yes Output break signal? Yes Clear DR bit to 0, set DDR bit to 1 Clear TE bit to 0 in SCR No No 4 End Figure 11.10 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev.3.00 Mar. 26, 2007 Page 371 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface In transmitting serial data, the SCI operates as follows. * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit in SCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD pin: Start bit: Transmit data: Stop bit: Mark state: One 0 bit is output. 7 or 8 bits are output, LSB first. One or two 1 bits (stop bits) are output. Output of 1 bits continues until the start bit of the next transmit data. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. * The SCI checks the TDRE flag when it outputs the stop bit. If the TDRE flag is 0, the SCI loads data from TDR into TSR, outputs the stop bit, then begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag in SSR to 1, outputs the stop bit, then continues output of 1 bits in the mark state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is requested at this time. Figure 11.11 shows an example of SCI transmit operation using a multiprocessor format. Multiprocessor bit 1 Multiprocessor bit Data D0 D1 D7 0/1 Stop bit 1 1 Start bit 0 Data D0 D1 D7 0/1 Stop Start bit bit 1 0 Serial data Idle (mark) state TDRE TEND TXI request TXI interrupt handler writes data in TDR and clears TDRE flag to 0 1 frame TXI request TEI request Figure 11.11 Example of SCI Transmit Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev.3.00 Mar. 26, 2007 Page 372 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Receiving Multiprocessor Serial Data: Figure 11.12 shows a sample flowchart for receiving multiprocessor serial data and indicates the procedure to follow. Initialize Start receiving 1 Set MPIE bit to 1 in SCR 2 Read ORER and FER flags in SSR Yes FER ORER = 1 ? No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data from RDR No Own ID? Yes Read ORER and FER flags in SSR 3 1. SCI initialization: the receive data function of the RxD pin is selected automatically. 2. ID receive cycle: set the MPIE bit to 1 in SCR. 3. SCI status check and ID check: read SSR, check that the RDRF flag is set to 1, then read data from RDR and compare with the processor's own ID. If the ID does not match, set the MPIE bit to 1 again and clear the RDRF flag to 0. If the ID matches, clear the RDRF flag to 0. 4. SCI status check and data receiving: read SSR, check that the RDRF flag is set to 1, then read data from RDR. 5. Receive error handling and break detection: if a receive error occurs, read the ORER and FER flags in SSR to identify the error. After executing the necessary error handling, clear the ORER and FER flags both to 0. Receiving cannot resume while either the ORER or FER flag remains set to 1. When a framing error occurs, the RxD pin can be read to detect the break state. FER ORER = 1 ? No Read RDRF flag in SSR Yes 4 No RDRF = 1? Yes Read receive data from RDR No Finished receiving? Yes Clear RE bit to 0 in SCR End 5 Error handling (continued on next page) Figure 11.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev.3.00 Mar. 26, 2007 Page 373 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 5 Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Break? No Framing error handling Clear RE bit to 0 in SCR Yes Clear ORER and FER flags to 0 in SSR End Figure 11.12 Sample Flowchart for Receiving Multiprocessor Serial Data (2) Rev.3.00 Mar. 26, 2007 Page 374 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Figure 11.13 shows an example of SCI receive operation using a multiprocessor format. Start bit 0 1 Data (ID1) MPB D7 1 Stop Start Data (data1) bit bit 1 0 MPB D7 0 Stop bit 1 1 D0 D1 D0 D1 Idle (mark) state MPIE RDRF RDR value RXI request RXI handler reads (multiprocessor RDR data and clears interrupt), MPIE = 0 RDRF flag to 0 ID1 Not own ID, so MPIE bit is set to 1 again No RXI request, RDR not updated a. Own ID does not match data 1 Start bit 0 Data (ID2) MPB D7 1 Stop Start bit bit 1 0 Data (data2) MPB Stop bit 1 1 D0 D1 D0 D1 D7 0 Idle (mark) state MPIE RDRF RDR value ID1 ID2 Data 2 RXI request RXI interrupt handler Own ID, so receiving MPIE bit is set (multiprocessor reads RDR data and continues, with data to 1 again interrupt), MPIE = 0 clears RDRF flag to 0 received by RXI interrupt handler b. Own ID matches data Figure 11.13 Example of SCI Receive Operation (8-Bit Data with Multiprocessor Bit and One Stop Bit) Rev.3.00 Mar. 26, 2007 Page 375 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.3.4 Synchronous Operation In synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver share the same clock but are otherwise independent, so full duplex communication is possible. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 11.14 shows the general format in synchronous serial communication. Transfer direction One unit (character or frame) of serial data * Serial clock LSB Serial data Don't care Note: * High except in continuous transmitting or receiving Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 11.14 Data Format in Synchronous Communication In synchronous serial communication, each data bit is placed on the communication line from one falling edge of the serial clock to the next. Data is guaranteed valid at the rise of the serial clock. In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In synchronous mode the SCI receives data by synchronizing with the rise of the serial clock. Communication Format The data length is fixed at 8 bits. No parity bit or multiprocessor bit can be added. Clock An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK pin can be selected by clearing or setting the CKE1 and CKE0 bits in SCR and the C/A bit in SMR. See table 11.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. Rev.3.00 Mar. 26, 2007 Page 376 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Transmitting and Receiving Data SCI Initialization (Synchronous Mode): Before transmitting or receiving, clear the TE and RE bits to 0 in SCR, then initialize the SCI as follows. When changing the communication mode or format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing the TE bit to 0 sets the TDRE flag to 1 and initializes TSR. Clearing the RE bit to 0, however, does not initialize the RDRF, PER, FER, and ORE flags and RDR, which retain their previous contents. Figure 11.15 shows a sample flowchart for initializing the SCI. Start of initialization Clear TE and RE bits to 0 in SCR Set CKE1 and CKE0 bits in SCR (leaving TE and RE bits cleared to 0) 1 1. Select the clock source in SCR. Clear the RIE, TIE, TEIE, MPIE, TE, and RE bits to 0. 2. Select the communication format in SMR. 3. Write the value corresponding to the bit rate in BRR. This step is not necessary when an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set the TE or RE bit to 1 in SCR. Also set the RIE, TIE, and TEIE bits as necessary. Setting the TE or RE bit enables the SCI to use the TxD or RxD pin. Note: In simultaneous transmitting and receiving, the TE and RE bits should be cleared to 0 or set to 1 simultaneously. 2 Select communication format in SMR 3 Set value in BRR Wait 1 bit interval elapsed? Yes Set TE or RE to 1 in SCR Set RIE, TIE, and TEIE bits as necessary No 4 Start transmitting or receiving Figure 11.15 Sample Flowchart for SCI Initialization Rev.3.00 Mar. 26, 2007 Page 377 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Transmitting Serial Data (Synchronous Mode): Figure 11.16 shows a sample flowchart for transmitting serial data and indicates the procedure to follow. 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. 3. To continue transmitting serial data: after checking that the TDRE flag is 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0. Initialize 1 Start transmitting Read TDRE flag in SSR 2 No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR All data transmitted? Yes No 3 Read TEND flag in SSR No TEND = 1? Yes Clear TE bit to 0 in SCR End Figure 11.16 Sample Flowchart for Serial Transmitting Rev.3.00 Mar. 26, 2007 Page 378 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface In transmitting serial data, the SCI operates as follows. * The SCI monitors the TDRE flag in SSR. When the TDRE flag is cleared to 0 the SCI recognizes that TDR contains new data, and loads this data from TDR into TSR. * After loading the data from TDR into TSR, the SCI sets the TDRE flag to 1 and starts transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7). * The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds the TxD pin in the MSB state. If the TEIE bit in SCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. * After the end of serial transmission, the SCK pin is held in a constant state. Figure 11.17 shows an example of SCI transmit operation. Transmit direction Serial clock Serial data TDRE TEND TXI request Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TXI interrupt handler writes data in TDR and clears TDRE flag to 0 1 frame TXI request TEI request Figure 11.17 Example of SCI Transmit Operation Rev.3.00 Mar. 26, 2007 Page 379 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Receiving Serial Data (Synchronous Mode): Figure 11.18 shows a sample flowchart for receiving serial data and indicates the procedure to follow. When switching from asynchronous mode to synchronous mode, make sure that the ORER, PER, and FER flags are cleared to 0. If the FER or PER flag is set to 1 the RDRF flag will not be set and both transmitting and receiving will be disabled. No SCI initialization: the receive data function of the RxD pin is selected automatically. 2., 3. Receive error handling: if a receive error Start receiving occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag Read ORER flag in SSR 2 remains set to 1. 4. SCI status check and receive data read: read SSR, check that the RDRF flag is set to 1, Yes ORER = 1? then read receive data from RDR and clear 3 the RDRF flag to 0. Notification that the RDRF Error handling No flag has changed from 0 to 1 can also be given by the RXI interrupt. (continued on next page) 5. To continue receiving serial data: check the Read RDRF flag in SSR 4 RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. RDRF = 1? Yes Read receive data from RDR, and clear RDRF flag to 0 in SSR Initialize 1 1. No Finished receiving? Yes Clear RE bit to 0 in SCR 5 End Figure 11.18 Sample Flowchart for Serial Receiving (1) Rev.3.00 Mar. 26, 2007 Page 380 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 3 Error handling Overrun error handling Clear ORER flag to 0 in SSR End Figure 11.18 Sample Flowchart for Serial Receiving (2) In receiving, the SCI operates as follows. * The SCI synchronizes with serial clock input or output and initializes internally. * Receive data is stored in RSR in order from LSB to MSB. After receiving the data, the SCI checks that the RDRF flag is 0 so that receive data can be transferred from RSR to RDR. If this check passes, the RDRF flag is set to 1 and the received data is stored in RDR. If the check does not pass (receive error), the SCI operates as indicated in table 11.11. If any receive error is detected, the subsequent data transmission/reception is disabled. * After setting the RDRF flag to 1, if the RIE bit is set to 1 in SCR, the SCI requests a receivedata-full interrupt (RXI). If the ORER flag is set to 1 and the RIE bit in SCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Rev.3.00 Mar. 26, 2007 Page 381 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Figure 11.19 shows an example of SCI receive operation. Receive direction Serial clock Serial data RDRF Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 ORER RXI request RXI interrupt handler reads data in RDR and clears RDRF flag to 0 1 frame RXI request Overrun error, ERI request Figure 11.19 Example of SCI Receive Operation Transmitting and Receiving Serial Data Simultaneously (Synchronous Mode): Figure 11.20 shows a sample flowchart for transmitting and receiving serial data simultaneously and indicates the procedure to follow. Rev.3.00 Mar. 26, 2007 Page 382 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Initialize Start transmitting and receiving 1 Read TDRE flag in SSR No TDRE = 1? Yes Write transmit data in TDR and clear TDRE flag to 0 in SSR 2 Read ORER flag in SSR Yes ORER = 1? 3 No Read RDRF flag in SSR No RDRF = 1? Yes Read receive data from RDR and clear RDRF flag to 0 in SSR Error handling 4 1. SCI initialization: the transmit data output function of the TxD pin and receive data input function of the RxD pin are selected, enabling simultaneous transmitting and receiving. 2. SCI status check and transmit data write: read SSR, check that the TDRE flag is 1, then write transmit data in TDR and clear the TDRE flag to 0. Notification that the TDRE flag has changed from 0 to 1 can also be given by the TXI interrupt. 3. Receive error handling: if a receive error occurs, read the ORER flag in SSR, then after executing the necessary error handling, clear the ORER flag to 0. Neither transmitting nor receiving can resume while the ORER flag remains set to 1. 4. SCI status check and receive data read: read SSR, check that the RDRF flag is 1, then read receive data from RDR and clear the RDRF flag to 0. Notification that the RDRF flag has changed from 0 to 1 can also be given by the RXI interrupt. 5. To continue transmitting and receiving serial data: check the RDRF flag, read RDR, and clear the RDRF flag to 0 before the MSB (bit 7) of the current frame is received. Also check that the TDRE flag is set to 1, indicating that data can be written, write data in TDR, then clear the TDRE flag to 0 before the MSB (bit 7) of the current frame is transmitted. No End of transmitting and receiving? Yes Clear TE and RE bits to 0 in SCR 5 End Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear the TE and RE bits both to 0, then set the TE and RE bits both to 1. Figure 11.20 Sample Flowchart for Serial Transmitting Rev.3.00 Mar. 26, 2007 Page 383 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.4 SCI Interrupts The SCI has four interrupt request sources: TEI (transmit-end interrupt), ERI (receive-error interrupt), RXI (receive-data-full interrupt), and TXI (transmit-data-empty interrupt). Table 11.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in SCR. Each interrupt request is sent separately to the interrupt controller. The TXI interrupt is requested when the TDRE flag is set to 1 in SSR. The TEI interrupt is requested when the TEND flag is set to 1 in SSR. The RXI interrupt is requested when the RDRF flag is set to 1 in SSR. The ERI interrupt is requested when the ORER, PER, or FER flag is set to 1 in SSR. Table 11.12 SCI Interrupt Sources Interrupt ERI RXI TXI TEI Description Receive error (ORER, FER, or PER) Receive data register full (RDRF) Transmit data register empty (TDRE) Transmit end (TEND) Low Priority High Rev.3.00 Mar. 26, 2007 Page 384 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 11.5 Usage Notes Note the following points when using the SCI. TDR Write and TDRE Flag The TDRE flag in SSR is a status flag indicating the loading of transmit data from TDR into TSR. The SCI sets the TDRE flag to 1 when it transfers data from TDR to TSR. Data can be written into TDR regardless of the state of the TDRE flag. If new data is written in TDR when the TDRE flag is 0, the old data stored in TDR will be lost because this data has not yet been transferred to TSR. Before writing transmit data in TDR, be sure to check that the TDRE flag is set to 1. Simultaneous Multiple Receive Errors Table 11.13 indicates the state of SSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs the RSR contents are not transferred to RDR, so receive data is lost. Table 11.13 SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 x x x Receive Data Transfer RSR RDR x Receive Errors Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. x: Receive data is not transferred from RSR to RDR. Rev.3.00 Mar. 26, 2007 Page 385 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Break Detection and Processing Break signals can be detected by reading the RxD pin directly when a framing error (FER) is detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. In the break state the SCI receiver continues to operate, so if the FER flag is cleared to 0 it will be set to 1 again. Sending a Break Signal When the TE bit is cleared to 0 the TxD pin becomes an I/O port, the level and direction (input or output) of which are determined by DR and DDR bits. This feature can be used to send a break signal. After the serial transmitter is initialized, the DR value substitutes for the mark state until the TE bit is set to 1 (the TxD pin function is not selected until the TE bit is set to 1). The DDR and DR bits should therefore both be set to 1 beforehand. To send a break signal during serial transmission, clear the DR bit to 0, then clear the TE bit to 0. When the TE bit is cleared to 0 the transmitter is initialized, regardless of its current state, so the TxD pin becomes an input/output port outputting the value 0. Receive Error Flags and Transmitter Operation (Synchronous Mode Only) When a receive error flag (ORER, PER, or FER) is set to 1 the SCI will not start transmitting, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing the RE bit to 0 does not clear the receive error flags to 0. Receive Data Sampling Timing in Asynchronous Mode and Receive Margin In asynchronous mode the SCI operates on a base clock with 16 times the bit rate frequency. In receiving, the SCI synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 11.21. Rev.3.00 Mar. 26, 2007 Page 386 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 16 clocks 8 clocks 0 Internal base clock 7 15 0 7 15 0 Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 11.21 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation (1). M = | ( 0.5 - 1 | D - 0.5 | ) - (L - 0.5) F (1 + F) | x 100% ..........(1) 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0 to 1.0) Frame length (L = 9 to 12) Absolute deviation of clock frequency From equation (1), if F = 0 and D = 0.5 the receive margin is 46.875%, as given by equation (2). When D = 0.5, F = 0: M = [0.5 - 1/(2 x 16)] x 100% = 46.875%..........................................................................................(2) This is a theoretical value. A reasonable margin to allow in system design is 20% to 30%. Rev.3.00 Mar. 26, 2007 Page 387 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Restrictions in Synchronous Mode When data transmission is performed using an external clock source as the serial clock, an interval of at least 5 states is necessary between clearing the TDRE flag in SSR and the start (falling edge) of the first transmit clock pulse corresponding to each frame (figure 11.22). This interval is also necessary when performing continuous transmission. If this condition is not satisfied, an operation error may occur. SCK t* TDRE t* TXD X0 X1 X2 X3 X4 X5 X6 X7 Y0 Y1 Y2 Y3 Note: * Make sure that t is at least 5 states. Continuous transmission Figure 11.22 Transmission in Synchronous Mode (Example) Rev.3.00 Mar. 26, 2007 Page 388 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface Restrictions when Switching from SCK Pin to Port Function in Synchronous SCI 1. Problem in Operation After setting DDR and DR to 1 and using synchronous SCI clock output, when the SCK pin is switched to the port function at the end of transmission, a low-level signal is output for one half-cycle before the port output state is established. When switching to the port function by making the following settings while DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, low-level output occurs for one half-cycle. (1) End of serial data transmission (2) TE bit = 0 (3) C/A bit = 0 ... switchover to port output (4) Occurrence of low-level output (see figure 11.23) Half-cycle low-level output occurs SCK/port (1) End of transmission Data TE (3) C/A = 0 C/A CKE1 CKE0 Bit 6 Bit 7 (2) TE = 0 (4) Low-level output Figure 11.23 Operation when Switching from SCK Pin Function to Port Pin Function Rev.3.00 Mar. 26, 2007 Page 389 of 682 REJ09B0353-0300 Section 11 Serial Communication Interface 2. Usage Note The procedure shown below should be used to prevent low-level output when switching from the SCK pin function to the port function. As this procedure temporarily places the SCK pin in the input state, the SCK/port pin should be pulled up beforehand with an external circuit. With DDR = 1, DR = 1, C/A = 1, CKE1 = 0, CKE0 = 0, and TE = 1, make the following settings in the order shown. (1) End of serial data transmission (2) TE bit = 0 (3) CKE1 bit = 1 (4) C/A bit = 0 ... switchover to port output (5) CKE1 bit = 0 High-level output SCK/port (1) End of transmission Data TE (4) C/A = 0 C/A (3) CKE1 = 1 CKE1 CKE0 (5) CKE1 = 0 Bit 6 Bit 7 (2) TE = 0 Figure 11.24 Operation when Switching from SCK Pin Function to Port Pin Function (Preventing Low-Level Output) Rev.3.00 Mar. 26, 2007 Page 390 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Section 12 Smart Card Interface 12.1 Overview SCI0 supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 12.1.1 Features Features of the Smart Card interface supported by the H8/3039 Group are as follows. * Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * On-chip baud rate generator allows any bit rate to be selected * Three interrupt sources Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently Rev.3.00 Mar. 26, 2007 Page 391 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD0 RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR Baud rate generator /4 /16 /64 Clock TxD0 Parity generation Parity check SCK0 TXI RXI ERI Legend: SCMR: Smart Card mode register RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register BRR: Bit rate register Figure 12.1 Block Diagram of Smart Card Interface Rev.3.00 Mar. 26, 2007 Page 392 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.1.3 Pin Configuration Table 12.1 shows the Smart Card interface pin configuration. Table 12.1 Smart Card Interface Pins Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 Abbreviation SCK0 RxD0 TxD0 I/O Output Input Output Function SCI0 clock output SCI0 receive data input SCI0 transmit data output 12.1.4 Register Configuration Table 12.2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, and RDR are the same as for the normal SCI function: see the register descriptions in section 11, Serial Communication Interface. Table 12.2 Smart Card Interface Registers Address* H'FFB0 H'FFB1 H'FFB2 H'FFB3 H'FFB4 H'FFB5 H'FFB6 1 Name Serial mode register Bit rate register Serial control register Transmit data register Serial status register Receive data register Smart card mode register Abbreviation SMR BRR SCR TDR SSR RDR SCMR R/W R/W R/W R/W R/W R/(W)* R R/W 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. Rev.3.00 Mar. 26, 2007 Page 393 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 12.2.1 Bit Initial value Read/Write Smart Card Mode Register (SCMR) 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Reserved bits Smart card interface mode select Enables or disables the smart card interface function Smart card data invert Inverts data logic levels Smart card data transfer direction Selects the serial/parallel conversion format SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 1 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Rev.3.00 Mar. 26, 2007 Page 394 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 12.3.4, Register Settings. Bit 2 SINV 0 1 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) Bit 1--Reserved: This bit cannot be modified and is always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): This bit enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 395 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.2.2 Bit Serial Status Register (SSR) 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value R/W Transmit end Status flag indicating end of transmission Error signal status Status flag indicating that an error signal has been received Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5--Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial Status Register (SSR). Bit 4--Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description Indicates normal data transmission, with no error signal returned [Clearing conditions] * * 1 Upon reset, in standby mode, or in module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) Indicates that the receiving device sent an error signal reporting a parity error [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. Rev.3.00 Mar. 26, 2007 Page 396 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Bits 3 to 0--Operate in the same way as for the normal SCI. For details, see section 11.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit are as shown below. Bit 2 TEND 0 Description Transmission is in progress [Clearing condition] When 0 is written to TDRE after reading TDRE = 1 1 End of transmission [Setting conditions] * * * Upon reset and in standby mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character (Initial value) Note: etu: Elementary Time Unit (time for transfer of 1 bit) 12.3 12.3.1 Operation Overview The main functions of the Smart Card interface are as follows. * One frame consists of 8-bit and plus a parity bit. * In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. * If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. * If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. * Only asynchronous communication is supported; there is no clocked synchronous communication function. Rev.3.00 Mar. 26, 2007 Page 397 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.3.2 Pin Connections Figure 12.2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD0 pin and RxD0 pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK0 pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. VCC TxD0 RxD0 SCK0 Clock line Px (port) H8/3039 Group Chip Connected equipment Reset line Data line I/O CLK RST IC card Figure 12.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev.3.00 Mar. 26, 2007 Page 398 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.3.3 Data Format Figure 12.3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Start bit Data bits Parity bit Error signal Legend: Ds: D0 to D7: Dp: DE: Figure 12.3 Smart Card Interface Data Format Rev.3.00 Mar. 26, 2007 Page 399 of 682 REJ09B0353-0300 Section 12 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts a date transfer of one frame. The data frame starts with a start bit (Ds, low-level). Then 8 data bits (D0 to D7) and a parity bit (Dp) follows. [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. Rev.3.00 Mar. 26, 2007 Page 400 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.3.4 Register Settings Table 12.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 12.3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Note: Bit 7 0 BRR7 TIE TDR7 TDRE RDR7 -- --: Unused bit. Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 0 TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF SMR Setting: The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 12.3.5, Clock. BRR Setting: BRR is used to set the bit rate. See section 12.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 11, Serial Communication Interface. Bit CKE0 specifies the clock output. Set these bits to 0 if a clock is not to be output, or to 1 if a clock is to be output. Rev.3.00 Mar. 26, 2007 Page 401 of 682 REJ09B0353-0300 Section 12 Smart Card Interface SCMR Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). * Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. * Inverse convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8/3039 Group, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). Rev.3.00 Mar. 26, 2007 Page 402 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 12.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK0 pin. B= 1488 x 2 2n-1 x (N + 1) x 10 6 Where: N = Value set in BRR (0 N 255) B = Bit rate (bit/s) = Operating frequency* (MHz) n = See table 12.4 Table 12.4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Note: * If the gear function is used to divide the system clock frequency, use the divided frequency to calculate the bit rate. The equation above applies directly to 1/1 frequency division. Table 12.5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) (MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 13.00 17473.1 8736.6 5824.4 14.2848 19200.0 9600.0 6400.0 16.00 21505.4 10752.7 7168.5 18.00 24193.5 12096.8 8064.5 Note: Bit rates are rounded off to one decimal place. Rev.3.00 Mar. 26, 2007 Page 403 of 682 REJ09B0353-0300 Section 12 Smart Card Interface The method of calculating the value from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 N 255, and the smaller error is specified. N= 1488 x 2 2n-1 xB x 10 - 1 6 Table 12.6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0) (MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 N Error 1 30 10.7136 N Error 1 25 13.00 N Error 1 8.99 14.2848 N Error 1 0.00 16.00 N Error 1 12.01 18.00 N Error 2 15.99 Table 12.7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 N 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( 1488 x 2 2n-1 x B x (N + 1) x 10 - 1) x 100 6 Rev.3.00 Mar. 26, 2007 Page 404 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.3.6 Data Transfer Operations Initialization Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD0 and RxD0 pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK0 pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. Rev.3.00 Mar. 26, 2007 Page 405 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Serial Data Transmission As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 12.4 shows an example of the transmission processing flow, and figure 12.5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. For details, see the following Interrupt Operations. Rev.3.00 Mar. 26, 2007 Page 406 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Start Initialization Start transmission ERS = 0? Yes No Error processing No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit to 0 End Figure 12.4 Example of Transmission Processing Flow Rev.3.00 Mar. 26, 2007 Page 407 of 682 REJ09B0353-0300 Section 12 Smart Card Interface TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data has been completed. Figure 12.5 Relation Between Transmit Operation and Internal Registers Serial Data Reception Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 12.6 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either flag is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Rev.3.00 Mar. 26, 2007 Page 408 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF = 1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 12.6 Example of Reception Processing Flow With the above processing, interrupt servicing is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. For details, see Interrupt Operation below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Rev.3.00 Mar. 26, 2007 Page 409 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Mode Switching Operation When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Interrupt Operation There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 12.8. Table 12.8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Mask Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI Rev.3.00 Mar. 26, 2007 Page 410 of 682 REJ09B0353-0300 Section 12 Smart Card Interface 12.4 Usage Note The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode In smart card interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 12.7. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 12.7 Receive Data Sampling Timing in Smart Card Mode Rev.3.00 Mar. 26, 2007 Page 411 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Thus the reception margin in smart card interface mode is given by the following formula. M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100% Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev.3.00 Mar. 26, 2007 Page 412 of 682 REJ09B0353-0300 Section 12 Smart Card Interface Retransfer Operations Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. * Retransfer operation when SCI is in receive mode Figure 12.8 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] [3] [4] Retransferred frame Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 Figure 12.8 Retransfer Operation in SCI Receive Mode Rev.3.00 Mar. 26, 2007 Page 413 of 682 REJ09B0353-0300 Section 12 Smart Card Interface * Retransfer operation when SCI is in transmit mode Figure 12.9 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] ERS [6] [8] [9] Transfer to TSR from TDR Transfer to TSR from TDR Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Transfer frame n+1 Ds D0 D1 D2 D3 D4 Figure 12.9 Retransfer Operation in SCI Transmit Mode Rev.3.00 Mar. 26, 2007 Page 414 of 682 REJ09B0353-0300 Section 13 A/D Converter Section 13 A/D Converter 13.1 Overview The H8/3039 Group includes a 10-bit successive-approximations A/D converter with a selection of up to eight analog input channels. When the A/D converter is not used, it can be halted independently to conserve power. For details see section 17.6, Module Standby Function. 13.1.1 Features A/D converter features are listed below. * 10-bit resolution * Eight input channels * Selectable analog conversion voltage range The analog voltage conversion range can be programmed by input of an analog reference voltage at the AVCC pin. * High-speed conversion Conversion time: minimum 7.4 s per channel (with 18 MHz system clock) * Two conversion modes Single mode: A/D conversion of one channel Scan mode: continuous conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * A/D conversion can be externally triggered * A/D interrupt requested at end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. Rev.3.00 Mar. 26, 2007 Page 415 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the A/D converter. Module data bus Bus interface ADDRC ADDRD ADDRA ADDRB ADCSR Internal data bus AVCC 10-bit D/A AV SS Successiveapproximations register AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Analog multiplexer + - Comparator Control circuit Sample-andhold circuit /16 /8 ADCR ADTRG Legend: ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: ADI interrupt A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 13.1 A/D Converter Block Diagram Rev.3.00 Mar. 26, 2007 Page 416 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.1.3 Input Pins Table 13.1 summarizes the A/D converter's input pins. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply for the analog circuits in the A/D converter. Table 13.1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin Abbreviation AVCC AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG I/O Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog power supply and reference voltage Analog ground and reference voltage Group 0 analog inputs Rev.3.00 Mar. 26, 2007 Page 417 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.1.4 Register Configuration Table 13.2 summarizes the A/D converter's registers. Table 13.2 A/D Converter Registers Address* H'FFE0 H'FFE1 H'FFE2 H'FFE3 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 1 Name A/D data register A (high) A/D data register A (low) A/D data register B (high) A/D data register B (low) A/D data register C (high) A/D data register C (low) A/D data register D (high) A/D data register D (low) A/D control/status register A/D control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR R/W R R R R R R R R R/(W)* R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'7F Notes: 1. Lower 16 bits of the address 2. Only 0 can be written in bit 7 to clear the flag. Rev.3.00 Mar. 26, 2007 Page 418 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.2 13.2.1 Bit ADDRn Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value Read/Write (n = A to D) A/D conversion data 10-bit data giving an A/D conversion result Reserved bits The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D data register are reserved bits that always read 0. Table 13.3 indicates the pairings of analog input channels and A/D data registers. The CPU can always read the A/D data registers. The upper byte can be read directly, but the lower byte is read through a temporary register (TEMP). For details see section 13.3, CPU Interface. The A/D data registers are initialized to H'0000 by a reset and in standby mode. Table 13.3 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev.3.00 Mar. 26, 2007 Page 419 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.2.2 Bit A/D Control/Status Register (ADCSR) 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value Read/Write Channel select 2 to 0 These bits select analog input channels Clock select Selects the A/D conversion time Scan mode Selects single mode or scan mode A/D start Starts or stops A/D conversion A/D interrupt enable Enables and disables A/D end interrupts A/D end flag Indicates end of A/D conversion Note: * Only 0 can be written to clear the flag. ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter. ADCSR is initialized to H'00 by a reset and in standby mode. Bit 7--A/D End Flag (ADF): Indicates the end of A/D conversion. Bit 7 ADF 0 1 Description [Clearing condition] Cleared by reading ADF while ADF = 1, then writing 0 in ADF [Setting conditions] * * Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels (Initial value) Rev.3.00 Mar. 26, 2007 Page 420 of 682 REJ09B0353-0300 Section 13 A/D Converter Bit 6--A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D end interrupt request (ADI) is disabled A/D end interrupt request (ADI) is enabled (Initial value) Bit 5--A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. Bit 5 ADST 0 1 Description A/D conversion is stopped (Initial value) Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode. Bit 4--Scan Mode (SCAN): Selects single mode or scan mode. For further information on operation in these modes, see section 13.4, Operation. Clear the ADST bit to 0 before switching the conversion mode. Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Clock Select (CKS): Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. Bit 3 CKS 0 1 Description Conversion time = 266 states (maximum) Conversion time = 134 states (maximum) (Initial value) Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Rev.3.00 Mar. 26, 2007 Page 421 of 682 REJ09B0353-0300 Section 13 A/D Converter Group Selection CH2 0 Channel Selection CH1 0 CH0 0 1 1 0 1 Single Mode AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 0 0 1 1 0 1 13.2.3 Bit A/D Control Register (ADCR) 7 TRGE 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- Reserved bits Trigger enable Enables or disables external triggering of A/D conversion 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value Read/Write ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'7F by a reset and in standby mode. Bit 7--Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion. Bit 7 TRGE 0 1 Description A/D conversion cannot be externally triggered (Initial value) A/D conversion starts at the falling edge of the external trigger signal (ADTRG) Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 422 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.3 CPU Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus. Therefore, although the upper byte can be accessed directly by the CPU, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 13.2 shows the data flow for access to an A/D data register. Upper-byte read CPU (H'AA) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower-byte read CPU (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 13.2 A/D Data Register Access Operation (Reading H'AA40) Rev.3.00 Mar. 26, 2007 Page 423 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 13.4.1 Single Mode (SCAN = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. When the mode or analog input channel must be switched during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 13.3 shows a timing diagram for this example. 1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The routine reads ADCSR, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRB). 7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps 2 to 7 are repeated. Rev.3.00 Mar. 26, 2007 Page 424 of 682 REJ09B0353-0300 Set * ADIE A/D conversion starts Clear * Clear * Set * Set * ADST ADF Idle State of channel 0 (AN 0) Idle A/D conversion (1) State of channel 1 (AN 1) Idle Idle A/D conversion (2) Idle State of channel 2 (AN 2) Idle State of channel 3 (AN 3) ADDRA Read conversion result A/D conversion result (1) Read conversion result A/D conversion result (2) ADDRB Figure 13.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ADDRC ADDRD Rev.3.00 Mar. 26, 2007 Page 425 of 682 REJ09B0353-0300 Section 13 A/D Converter Note: * Vertical arrows ( ) indicate instructions executed by software. Section 13 A/D Converter 13.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 13.4 shows a timing diagram for this example. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev.3.00 Mar. 26, 2007 Page 426 of 682 REJ09B0353-0300 Continuous A/D conversion Set *1 Clear*1 ADST Clear* 1 A/D conversion time Idle A/D conversion (1) ADF Idle A/D conversion (4) Idle State of channel 0 (AN 0) Idle Idle A/D conversion (2) State of channel 1 (AN 1) Idle A/D conversion (3) A/D conversion (5)*2 Idle State of channel 2 (AN 2) Idle Transfer A/D conversion result (1) Idle State of channel 3 (AN 3) ADDRA A/D conversion result (4) ADDRB A/D conversion result (2) Figure 13.4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ADDRC A/D conversion result (3) ADDRD Rev.3.00 Mar. 26, 2007 Page 427 of 682 REJ09B0353-0300 Section 13 A/D Converter Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. Section 13 A/D Converter 13.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 13.5 shows the A/D conversion timing. Table 13.4 indicates the A/D conversion time. As indicated in figure 13.5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 13.4. In scan mode, the values given in table 13.4 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend: (1): ADCSR write cycle (2): ADCSR address tD : Synchronization delay t SPL : Input sampling time t CONV: A/D conversion time Figure 13.5 A/D Conversion Timing Rev.3.00 Mar. 26, 2007 Page 428 of 682 REJ09B0353-0300 Section 13 A/D Converter Table 13.4 A/D Conversion Time (Single Mode) CKS = 0 Symbol Synchronization delay Input sampling time A/D conversion time tD tSPL tCONV Min 10 -- 259 Typ -- 63 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 31 -- Max 9 -- 134 Note: Values in the table are numbers of states. 13.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit had been set to 1 by software. Figure 13.6 shows the timing. ADTRG Internal trigger signal ADST A/D conversion Figure 13.6 External Trigger Input Timing Rev.3.00 Mar. 26, 2007 Page 429 of 682 REJ09B0353-0300 Section 13 A/D Converter 13.5 Interrupts The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. 13.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AVSS ANn AVCC. (2) Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. If conditions (1) and (2) above are not met, the reliability of the device may be adversely affected. Notes on Board Design In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), and analog power supply and reference voltage (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog power supply (AVCC) should be connected between AVCC and AVSS as shown in figure 13.7. Also, the bypass capacitors connected to AVCC and the filter capacitor connected to AN0 to AN7 must be connected to AVSS. Rev.3.00 Mar. 26, 2007 Page 430 of 682 REJ09B0353-0300 Section 13 A/D Converter If a filter capacitor is connected as shown in figure 13.7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Therefore careful consideration is required when deciding the circuit constants. AVCC Rin*2 *1 100 AN0 to AN7 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 13.7 Example of Analog Input Protection Circuit Table 13.5 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Note: * Min -- -- Max 20 10* Unit pF k When VCC = 4.0 V to 5.5 V and 12 MHz Rev.3.00 Mar. 26, 2007 Page 431 of 682 REJ09B0353-0300 Section 13 A/D Converter 10 k AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 13.8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions H8/3039 Group A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 13.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 13.10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 13.9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. Rev.3.00 Mar. 26, 2007 Page 432 of 682 REJ09B0353-0300 Section 13 A/D Converter Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 8 2 8 3 8 4 8 5 8 6 8 7 8 FS Analog input voltage Figure 13.9 A/D Conversion Precision Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 13.10 A/D Conversion Precision Definitions (2) Rev.3.00 Mar. 26, 2007 Page 433 of 682 REJ09B0353-0300 Section 13 A/D Converter Permissible Signal Source Impedance H8/3039 Group analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. When converting in the single mode, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., voltage regulation 5 mV/s or greater). When converting a high-speed analog signal and when performing conversion in the scan mode, a low-impedance buffer should be inserted. Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, thus acting as antennas. H8/3039 Group Sensor output impedance Up to 10 k Sensor input Low-pass filter C Up to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Note: Values are reference values. Figure 13.11 Example of Analog Input Circuit Rev.3.00 Mar. 26, 2007 Page 434 of 682 REJ09B0353-0300 Section 14 RAM Section 14 RAM 14.1 Overview The H8/3039 has 4 kbytes of on-chip static RAM, H8/3038 has 2 kbytes, H8/3037 has 1 kbyte, and H8/3036 has 512 bytes. The RAM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte data and word data in two states, making the RAM suitable for rapid data transfer. The RAM enable bit (RAME) in the system control register (SYSCR) can enable or disable the on-chip RAM. Table 14.1 shows the address of the on-chip RAM in each operating mode. Table 14.1 The Address of the On-Chip RAM in Each Operating Mode Mode Modes 1, 5, 7 Mode 3 Mode 6 H8/3039 (4 kbytes) H'FEF10 to H'FFF0F H'FFEF10 to H'FFFF0F H'F710 to H'FF0F H8/3038 (2 kbytes) H'FF710 to H'FFF0F H'FFF710 to H'FFFF0F H'F710 to H'FF0F H8/3037 (1k byte) H'FFB10 to H'FFF0F H'FFFB10 to H'FFFF0F H'FB10 to H'FF0F H8/3036 (512 bytes) H'FFD10 to H'FFF0F H'FFFD10 to H'FFFF0F H'FD10 to H'FF0F Rev.3.00 Mar. 26, 2007 Page 435 of 682 REJ09B0353-0300 Section 14 RAM 14.1.1 Block Diagram Figure 14.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) Bus interface SYSCR H'FEF10* H'FEF12* H'FEF11* H'FEF13* On-chip RAM H'FFF0E* Even addresses Legend: SYSCR: System control register Note: * Lower 20 bits of the address H'FFF0F* Odd addresses Figure 14.1 RAM Block Diagram (H8/3039 in Modes 1, 5 and 7) 14.1.2 Register Configuration The on-chip RAM is controlled by the system control register (SYSCR). Table 14.2 gives the address and initial value of SYSCR. Table 14.2 RAM Control Register Address* H'FFF2 Note: * Name System control register Lower 16 bits of the address Abbreviation SYSCR R/W R/W Initial Value H'0B Rev.3.00 Mar. 26, 2007 Page 436 of 682 REJ09B0353-0300 Section 14 RAM 14.2 Bit System Control Register (SYSCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 -- 1 -- 0 RAME 1 R/W Initial value Read/Write RAM enable bit Enables or disables on-chip RAM Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 Software standby One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized at the rising edge of the input at the RES pin. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) Rev.3.00 Mar. 26, 2007 Page 437 of 682 REJ09B0353-0300 Section 14 RAM 14.3 Operation When the RAME bit is set to 1, the on-chip RAM is enabled. This LSI can access the on-chip RAM when addressing the addresses shown in table 14.1 in each operation mode. When the RAME bit is cleared to 0 in modes 1, 3, and 5 (expanded modes), external address space is accessed. When the RAME bit is cleared to 0 in modes 6 and 7 (single-chip modes), the on-chip RAM is not accessed. Read operation always reads H'FF and disables writing. The on-chip RAM is connected to the CPU by a 16-bit wide data bus and can be read and written on a byte or a word basis. Byte data can be accessed in two states using the higher 8 bits of the data bus. Word data beginning from an even address can be accessed in two states using the 16-bit data bus. Rev.3.00 Mar. 26, 2007 Page 438 of 682 REJ09B0353-0300 Section 15 ROM Section 15 ROM 15.1 Overview The H8/3039 has 128 kbytes of on-chip ROM (flash memory or mask ROM), the H8/3038 has 64 kbytes, the H8/3037 has 32 kbytes and H8/3036 has 16 kbytes. The ROM is connected to the CPU by a 16-bit data bus. The CPU accesses both byte and word data in two states, enabling rapid data transfer. The mode pins (MD2 to MD0) can be set to enable or disable the on-chip ROM. See table 15.1. The on-chip flash memory product (H8/3039F-ZTAT) can be erased and programmed on-board as well as with a general-purpose PROM programmer. Table 15.1 Operating Mode and ROM Mode Pins Mode Mode 1 (1-Mbyte expanded mode with on-chip ROM disabled) Mode 2 (1-Mbyte expanded mode with on-chip ROM disabled)* Mode 3 (16-Mbyte expanded mode with on-chip ROM disabled) MD2 0 0 0 MD1 0 1 1 0 0 1 1 MD0 1 0 1 0 1 0 1 Enabled On-Chip ROM Disabled (external address area) Mode 4 1 (16-Mbyte expanded mode with on-chip ROM disabled)* Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) Mode 6 (single-chip normal mode) Mode 7 (single-chip advanced mode) Note: * 1 1 1 Modes 2 and 4 cannot be used with this LSI. Do not set the mode pin to mode 2 or 4. Rev.3.00 Mar. 26, 2007 Page 439 of 682 REJ09B0353-0300 Section 15 ROM 15.2 15.2.1 Overview of Flash Memory Features The features of the flash memory are summarized below. * Four flash memory operating modes Program mode Erase mode Program-verify mode Erase-verify mode * Programming/erase methods The flash memory is programmed 32 bytes at a time. Erasing is performed by block erase. The block to be erased can be specified by setting the corresponding bit. There are block areas of 32 kbytes x 3 blocks, 28 kbytes x 1 block, and 1 kbyte x 4 blocks. * Programming/erase times The flash memory programming time is 10 ms (typ.) for simultaneous 32-byte programming, equivalent to 300 s (typ.) per byte, and the erase time is 100 ms (typ.) per block. * Reprogramming capability The flash memory can be reprogrammed up to 100 times. * On-board programming modes There are two modes in which flash memory can be programmed/erased/verified on-board: Boot mode User program mode * Automatic bit rate adjustment With data transfer in boot mode, the this LSI's bit rate can be automatically adjusted to match the transfer bit rate of the host (9600 bps and 4800 bps). * Flash memory emulation by RAM Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates in real time. * PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. * Protect modes There are three protect modes, hardware, software, and error protect, which allow protected status to be designated for flash memory program/erase/verify operations. Rev.3.00 Mar. 26, 2007 Page 440 of 682 REJ09B0353-0300 Section 15 ROM 15.2.2 Block Diagram Figure 15.1 shows a block diagram of the flash memory. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) FLMCR*2 EBR*2 RAMCR*2 FLMSR*2 H'00000 H'00002 H'00001 H'00003 Bus interface/controller Operating mode FWE pin*1 Mode pins On-chip Flash memory (128 kbytes) H'1FFFC H'1FFFD Legend: FLMCR: EBR: RAMCR: FLMSR: H'1FFFE H'1FFFF even address odd address Flash memory control register Erase block register RAM control register Flash memory status register Notes: 1. Functions as the FWE pin in the flash memory versions and as the RESO pin in the mask ROM versions. 2. The registers that control the flash memory versions (FLMCR, EBR, RAMCR, and FLMSR) are used in the flash memory versions only. They are not provided in the mask ROM versions. Reading the corresponding addresses in a mask ROM version will always return 1s, and writes to these addresses are disabled. Figure 15.1 Block Diagram of Flash Memory Rev.3.00 Mar. 26, 2007 Page 441 of 682 REJ09B0353-0300 Section 15 ROM 15.2.3 Pin Configuration The flash memory is controlled by means of the pins shown in table 15.2. Table 15.2 Flash Memory Pins Pin Name Reset Flash write enable Mode 2 Mode 1 Mode 0 Transmit data Receive data Abbreviation RES FWE* MD2 MD1 MD0 TxD1 RxD1 I/O Input Input Input Input Input Output Input Function Reset Flash program/erase protection by hardware Sets this LSI operating mode Sets this LSI operating mode Sets this LSI operating mode Serial transmit data output Serial receive data input Notes: The transmit data and receive data pins are used in boot mode. * In the mask ROM versions, the FWE pin functions as the RESO pin. 15.2.4 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 15.3. Table 15.3 Flash Memory Registers Register Name Flash memory control register Erase block register RAM control register Flash memory status register Abbreviation FLMCR EBR RAMCR FLMSR R/W R/W R/W R/W R Initial Value H'00* H'00 H'F1 H'7F 2 Address* H'FF40 H'FF42 H'FF47 H'FF4D 1 Notes: 1. Lower 16 bits of the address. 2. When a high level is input to the FWE pin, the initial value is H'80. The registers in table 15.3 are used in the flash memory versions only. Reading the corresponding addresses in a mask ROM version will always return 1s, and writes to these addresses are disabled. Rev.3.00 Mar. 26, 2007 Page 442 of 682 REJ09B0353-0300 Section 15 ROM 15.3 15.3.1 Register Descriptions Flash Memory Control Register (FLMCR) FLMCR is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1. Program mode is entered by setting SWE to 1 when FWE = 1, then setting the PSU bit, and finally setting the P bit. Erase mode is entered by setting SWE to 1 when FWE = 1, then setting the ESU bit, and finally setting the E bit. FLMCR is initialized by a reset, and in hardware standby mode and software standby mode. Its initial value is H'80 when a high level is input to the FWE pin, and H'00 when a low level is input. In mode 6 the FWE pin must be fixed low, as flash memory on-board programming is not supported. Therefore, bits in this register cannot be set to 1 in mode 6. When on-chip flash memory is disabled, a read will return H'00, and writes are invalid. When setting bits 6 to 0 in this register to 1, each bit should be set individually. Writes to the ESU, PSU, EV and PV bits in FLMCR are enabled only when FWE = 1 and SWE = 1; writes to the E bit only when FWE = 1, SWE = 1, and ESU = 1; and writes to the P bit only when FWE = 1, SWE = 1, and PSU = 1. Rev.3.00 Mar. 26, 2007 Page 443 of 682 REJ09B0353-0300 Section 15 ROM Bit Modes 1 to 4, and 6 7 FWE Initial value Read/Write 0 R 1/0 R 6 SWE 0 R 0 R/W 5 ESU 0 R 0 R/W 4 PSU 0 R 0 R/W 3 EV 0 R 0 R/W 2 PV 0 R 0 R/W 1 E 0 R 0 R/W 0 P 0 R 0 R/W Modes Initial value 5 and 7 Read/Write Program mode Designates transition to or exit from program mode Erase mode Designates transition to or exit from erase mode Program-verify mode Designates transition to or exit from program-verify mode Erase-verify mode Designates transition to or exit from erase-verify mode Program setup Prepares for a transition to program mode. Erase setup Prepares for a transition to erase mode. Software write enable bit Enables or disables the flash memory. Flash write enable bit Sets hardware protection against flash memory programming/erasing. Bit 7--Flash Write Enable Bit (FWE): Sets hardware protection against flash memory programming/erasing. When using this bit, refer to section 15.9, Notes on Flash Memory Programming/Erasing. Bit 7 FWE 0 1 Description When a low level is input to the FWE pin (hardware-protected state) When a high level is input to the FWE pin Rev.3.00 Mar. 26, 2007 Page 444 of 682 REJ09B0353-0300 Section 15 ROM Bit 6--Software Write Enable Bit (SWE)* * : This bit enables/disables flash memory programming/erasing. This bit should be set before setting FLMCR bits 5 to 0, and EBR bits 7 to 0. Do not set the ESU, PSU, EV, PV, E, or P bits at the same time. Bit 6 SWE 0 1 Description Program/erase disabled Program/erase enabled [Setting condition] When FWE = 1 1 1 2 (Initial value) Bit 5--Erase Setup Bit (ESU)* : Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU 0 1 Description Erase setup cleared Erase setup [Setting condition] When FWE = 1, and SWE = 1 1 (Initial value) Bit 4--Program Setup Bit (PSU)* : Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time. Bit 4 PSU 0 1 Description Program setup cleared Program setup [Setting condition] When FWE = 1, and SWE = 1 (Initial value) Rev.3.00 Mar. 26, 2007 Page 445 of 682 REJ09B0353-0300 Section 15 ROM Bit 3--Erase-Verify (EV)* : Selects erase-verify mode transition or clearing. Do not set the SWE, ESU, PSU, PV, E, or P bit at the same time. Bit 3 EV 0 1 Description Erase-verify mode cleared Transition to erase-verify mode [Setting condition] When FWE = 1, and SWE = 1 1 1 (Initial value) Bit 2--Program-Verify (PV)* : Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV 0 1 Description Program-verify mode cleared Transition to program-verify mode [Setting condition] When FWE = 1, and SWE = 1 1 3 (Initial value) Bit 1--Erase (E)* * : Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time. Bit 1 E 0 1 Description Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 (Initial value) Rev.3.00 Mar. 26, 2007 Page 446 of 682 REJ09B0353-0300 Section 15 ROM Bit 0--Program (P)* * : Selects program mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or E bit at the same time. Bit 0 P 0 1 Description Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 (Initial value) 1 3 Notes: 1. Do not set two or more bits at the same time. Do not turn off VCC when a bit is set. 2. Do not set/clear the SWE bit simultaneously with other bits (ESU, PSU, EV, PV, E, P). 3. Set the P and E bits according to the program and erase algorithms shown in section 15.5, Programming/Erasing Flash Memory. For the usage precautions, see section 15.9, Notes on Flash Memory Programming/Erasing. 15.3.2 Erase Block Register (EBR) EBR is an 8-bit register that designates the flash memory block for erasure. EBR is initialized to H'00 by a reset, in hardware standby mode, or software standby mode, when a high level is not input to the FWE terminal, or when the FLMCR SWE bit is 0 when a high level is applied to the FWE terminal. When a bit is set in EBR, the corresponding block can be erased. Other blocks are erase - protected. The blocks are erased block by block. Therefore, set only one bit in EBR; do not set bits in EBR to erase two or more blocks at the same time. Each bit in EBR cannot be set until the SWE bit in FLMCR is set. The flash memory block configuration is shown in table 15.4. To erase all the blocks, erase each block sequentially. This LSI does not support the on-board programming mode in mode 6, so bits in this register cannot be set to 1 in mode 6. Rev.3.00 Mar. 26, 2007 Page 447 of 682 REJ09B0353-0300 Section 15 ROM Bit 7 EB7 Modes 1 to 4, and 6 Modes 5 and 7 Initial value Read/Write Initial value Read/Write 0 R 0 R/W 6 EB6 0 R 0 R/W 5 EB5 0 R 0 R/W 4 EB4 0 R 0 R/W 3 EB3 0 R 0 R/W 2 EB2 0 R 0 R/W 1 EB1 0 R 0 R/W 0 EB0 0 R 0 R/W Bits 7 to 0--Block 7 to 0 (EB7 to EB0): These bits select blocks (EB7 to EB0) to be erased. Bits 7 to 0 EB7 to EB0 0 1 Description Block EB7 to EB0 is not selected. Block EB7 to EB0 is selected. (Initial value) Note: Set each bit of EBR to H'00 except when erasing. Table 15.4 Flash Memory Erase Blocks Block (Size) EB0 (1 kbyte) EB1 (1 kbyte) EB2 (1 kbyte) EB3 (1 kbyte) EB4 (28 kbytes) EB5 (32 kbytes) EB6 (32 kbytes) EB7 (32 kbytes) Address H'00000 to H'003FF H'00400 to H'007FF H'00800 to H'00BFF H'00C00 to H'00FFF H'01000 to H'07FFF H'08000 to H'0FFFF H'10000 to H'17FFF H'18000 to H'1FFFF Rev.3.00 Mar. 26, 2007 Page 448 of 682 REJ09B0353-0300 Section 15 ROM 15.3.3 RAM Control Register (RAMCR) RAMCR selects the RAM area used when emulating real-time reprogramming of the flash memory. Bit 7 -- Modes Initial value 1 to 4 Read/Write Modes Initial value 5 to 7 Read/Write 1 -- 1 -- 6 -- 1 -- 1 -- 5 -- 1 -- 1 -- 4 -- 1 -- 1 -- 3 RAMS 0 R 0 R/W* 2 RAM2 0 R 0 R/W* 1 RAM1 0 R 0 R/W* 0 -- 1 -- 1 -- Reserved bit RAM2/1 This bit is used with bit 3 to set the RAM area. RAM select This bit is used with bits 2 and 1 to set the RAM area. Reserved bits Note: * Cannot be set to 1 in mode 6. Bits 7 to 4--Reserved: These bits cannot be modified and are always read as 1. Bit 3--RAM Select (RAMS): Is used with bits 2 to 1 to reassign an area to RAM (see table 15.5). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled. It is initialized by a reset and in hardware standby mode. It is not initialized in software standby mode. When bit 3 is set, all flash-memory blocks are protected from programming and erasing. Bits 2 to 1--RAM2 to RAM1: These bits are used with bit 3 to reassign an area to RAM (see table 15.5). The initial setting for this bit is 0 in modes 5, 6, and 7 (internal flash memory enabled) and programming is enabled.* In modes other than 5 to 7, 0 is always read and writing is disabled. They are initialized by a reset and in hardware standby mode. They are not initialized in software standby mode. Rev.3.00 Mar. 26, 2007 Page 449 of 682 REJ09B0353-0300 Section 15 ROM Bit 0--Reserved: This bit cannot be modified and is always read as 1. Note: * Flash memory emulation by RAM is not supported for Mode 6 (single chip normal mode), so programming is possible, but do not set 1. When performing flash memory emulation by RAM, the RAME bit in SYSCR must be set to 1. Table 15.5 RAM Area Reassignment Bit 3 RAM Area H'FFF800 to H'FFFBFF H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF RAMS 0 1 1 1 1 Bit 2 RAM2 0/1 0 0 1 1 Bit 1 RAM1 0/1 0 1 0 1 RAM Emulation State No emulation Mapping RAM ROM area H'00000 H'003FF H'00400 ROM block H'007FF EB0-EB3 H'00800 (H'00000-H'00FFF) H'00BFF H'00C00 H'00FFF EB0 EB1 Mapping RAM EB2 EB3 ROM selection area RAM selection area RAM area H'FEF10 H'FF7FF Real RAM H'FF800 H'FFBFF H'FFC00 H'FFF0F RAM overlap area (H'FF800-H'FFBFF) Figure 15.2 Example of Overlap ROM Area and RAM Area Rev.3.00 Mar. 26, 2007 Page 450 of 682 REJ09B0353-0300 Section 15 ROM 15.3.4 Flash Memory Status Register (FLMSR) The flash memory status register (FLMSR) detects flash memory errors. Bit 7 FLER 6 -- 1 -- 5 -- 1 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value Read/Write 0 R -- Reserved bits Flash memory error Status flag indicating that an error was detected during programming or erasing Bit 7--Flash Memory Error (FLER): Indicates that an error occurred while flash memory was being programmed or erased. When bit 7 is set, flash memory is placed in an error-protect mode. Bit 7 FLER 0 Description Flash memory program/erase protection (error protection* ) is disabled [Clearing condition] WDT reset, reset by RES pin, or hardware standby mode 1 An error has occurred during flash memory programming/erasing 1 Flash memory program/erase protection (error protection* ) is enabled [Setting conditions] 1. Flash memory was read* while being programmed or erased (including vector or instruction fetch, but not including reading of a RAM area overlapped onto flash memory). 2. A hardware exception-handling sequence (other than a reset, invalid instruction, trap instruction, or zero-divide exception) was executed just before programming or 3 erasing.* 3. The SLEEP instruction (including software standby mode) was executed during programming or erasing. Notes: 1. For details, see section 15.6.3, Error Protection. 2. The read data has undetermined values. 3. Before stack and vector read by exception handling. 2 1 (Initial value) Bits 6 to 0--Reserved: These bits cannot be modified and are always read as 1. Rev.3.00 Mar. 26, 2007 Page 451 of 682 REJ09B0353-0300 Section 15 ROM 15.4 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 15.6. In mode 6 (on-chip ROM enabled) in this LSI, the boot mode and user program mode cannot be used. For the notes on FWE pin set/reset, see section 15.9, Notes on Flash Memory Programming/Erasing. Table 15.6 Setting On-Board Programming Modes Mode Boot mode mode 5 mode 7 User program mode mode 5 mode 7 FWE 1* 1 MD2 0* 0* 1 1 2 2 MD1 0 1 0 1 MD0 1 1 1 1 Notes 0: VIL 1: VIH Notes: 1. For the High level input timing, see items (6) and (7) of Notes on Using the Boot Mode. 2. In the boot mode, the MD2 setting becomes inverted input. In the boot mode, the mode control register (MDCR) can be used to monitor the status of modes 5 and 7 in the same way as in the normal mode. Rev.3.00 Mar. 26, 2007 Page 452 of 682 REJ09B0353-0300 Section 15 ROM On-Board Programming Modes * Boot mode 1. Initial state The flash memory is in the erased state when the device is shipped. The description here applies to the case where the old program version or data is being rewritten. The user should prepare the programming control program and new application program beforehand in the host. Host Programming control program New application program 2. Programming control program transfer When boot mode is entered, the boot program in this chip (originally incorporated in the chip) is started, an SCI communication check is carried out, and the boot program required for flash memory erasing is automatically transferred to the RAM boot program area. Host Programming control program New application program This chip Boot program Flash memory RAM SCI This chip Boot program Flash memory RAM Boot program area SCI Application program (old version) Application program (old version) 3. Flash memory initialization The erase program in the boot program area (in RAM) is executed, and the flash memory is initialized (to H'FF). In boot mode, entire flash memory erasure is performed, without regard to blocks. Host Programming control program New application program 4. Writing new application program The programming control program transferred from the host to RAM by SCI communication is executed, and the new application program in the host is written into the flash memory. Host This chip Boot program Flash memory RAM Boot program area Flash memory erase SCI This chip Boot program Flash memory RAM Programming control program New application program SCI Program execution state Figure 15.3 Boot Mode Rev.3.00 Mar. 26, 2007 Page 453 of 682 REJ09B0353-0300 Section 15 ROM * User program mode 1. Initial state (1) The program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer When the FWE pin is driven high, user software confirms this fact, executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM. Host Programming/ erase control program New application program This chip Boot program Flash memory Transfer program RAM SCI This chip Boot program Flash memory Transfer program Host New application program SCI RAM Programming/ erase control program Application program (old version) Application program (old version) 3. Flash memory initialization The programming/erase program in RAM is executed, and the flash memory is initialized (to H'FF). Erasing can be performed in block units, but not in byte units. Host 4. Writing new application program Next, the new application program in the host is written into the erased flash memory blocks. Do not write to unerased blocks. Host New application program This chip Boot program Flash memory FWE assessment program This chip SCI RAM Boot program Flash memory FWE assessment program Transfer program Programming/ erase control program Programming/ erase control program SCI RAM Transfer program Flash memory erase New application program Program execution state Figure 15.4 User Program Mode (Example) Rev.3.00 Mar. 26, 2007 Page 454 of 682 REJ09B0353-0300 Section 15 ROM 15.4.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. In reset start, after setting this LSI pin to the boot mode, start the microcomputer boot program, measure the Low period of the data sent from the host, and select the bit rate register (BRR) value beforehand. Then enable reception of the user program from the outside using the serial communication interface (SCI) on this LSI, and write the received user program to on-chip RAM. After the program has been stored the end of writing, execution branches to the top address (H'FF300) of the on-chip RAM, execute the program written on the on-chip RAM, and enable flash memory program/erase. The system configuration in boot mode is shown in figure 15.5, and the boot program mode execution procedure in figure 15.6. This LSI Flash memory Host Write data reception Verify data transmission RXD1 SCI1 TXD1 On-chip RAM Figure 15.5 System Configuration in Boot Mode Rev.3.00 Mar. 26, 2007 Page 455 of 682 REJ09B0353-0300 Section 15 ROM Start Set pins to boot program mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate This LSI measures low period of H'00 data transmitted by host 1 2 1 2 Set this LSI to the boot mode and reset starts the LSI. Set the host to the prescribed bit rate (4800, 9600) and consecutively send H'00 data in 8-bit data, 1 stop bit format. This LSI repeatedly measures the RXD1 pin Low period and calculates the asynchronous communication bit rate at which the host performs transfer. At the end of SCI bit rate adjustment, this LSI sends one byte of H'00 data to signal the end of adjustment. Check if the host normally received the one byte bit rate adjustment end signal sent from this LSI and sent one byte of H'55 data. After H'55 is sent, the host receives H'AA and sends the byte count of the user program that is transferred to this LSI. Send the 2-byte count in upper byte and lower byte order. Then sequentially send the program set by the user. This LSI sequentially sends (echo back) each byte of the received byte count and user program to the host as verification data. This LSI sequentially writes the received user program to the on-chip RAM area (H'FF300-H'FFEFF). Before executing the transferred user program, this LSI checks if data was written to flash memory after control branched to the RAM boot program area (H'FEF10-H'FF2FF). If data was already written to flash memory, all the blocks are erased. After sending H'AA, this LSI branches to the on-chip RAM area (H'FF300) and executes the user program written to that area. 3 3 This LSI calculates bit rate and sets value in bit rate register After bit rate adjustment, this LSI transmits one byte of H'00 data to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one byte of H'55 data After receiving H'55, this LSI sends H'AA and receives two bytes of the byte count (N) of the program transferred to the on-chip RAM.*1 4 4 5 5 6 6 This LSI transfers the user program to RAM.*2 7 7 This LSI calculates the remaining number of bytes to be sent (N = N - 1). Transfer end byte count N = 0? Yes After branching to the RAM boot program area (H'FEF10 to H'FF2FF), this LSI checks the data in the flashmemory user area. No 8 9 8 All data = H'FF? Yes No Notes: 1. The RAM area that can be used by the user is 3.0 kbytes. Set the transfer byte count to within 3.0 kbytes. Always send the 2-byte transfer byte count in upper byte and lower byte order. Transfer byte count example: For 256 bytes (H'0100), upper byte H'01, lower byte H'00. 2. Set the part that controls the user program flash memory at the program according to the flash memory programming/erase algorithms described later. 3. When a memory cell malfunctions and cannot be erased, this LSI sends one H'FF byte as an erase error and stops the erase operation and subsequent operations. Erase all blocks of flash memory.*3 9 After sending H'AA, this LSI branches to the RAM area (H'FF300) and executes the user program transferred to the RAM. Figure 15.6 Boot Mode Execution Procedure Rev.3.00 Mar. 26, 2007 Page 456 of 682 REJ09B0353-0300 Section 15 ROM Automatic SCI Bit Rate Adjustment Start bit D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Low period (9 bits) measured (H'00 data) High period (1 or more bits) Figure 15.7 Measuring the Low Period of the Communication Data from the Host When boot mode is initiated, this LSI measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host (figure 15.7). The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. This LSI calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the LSI. If reception cannot be performed normally, initiate boot mode again (reset), and repeat the above operations. Depending on the host's transmission bit rate and the system clock frequency of this LSI, there will be a discrepancy between the bit rates of the host and the LSI. To ensure correct SCI operation, the host's transfer bit rate should be set to 4800 and 9600 1 bps* . Table 15.7 shows typical host transfer bit rates and system clock frequencies for which automatic adjustment of this LSI bit rate is possible. The boot program should be executed within this system 2 clock range* . Table 15.7 System Clock Frequencies for which Automatic Adjustment of This LSI Bit Rate Is Possible Host Bit Rate (bps) 9600 4800 System Clock Frequency for which Automatic Adjustment of This LSI Bit Rate Is Possible (MHz) 8 to 18 4 to 18 Notes: 1. The host bit rate settings are 4800 and 9600bps only. Do not use any other setting. 2. This LSI may automatically adjusts the bit rate except for bit rate and system clock combinations as shown in table 15.7. However, the bit rate of the host and this LSI will be different and subsequent transfers will not be carried out normally. Therefore, always execute the boot mode within the range of the bit rate and system clock combinations shown in table 15.7. Rev.3.00 Mar. 26, 2007 Page 457 of 682 REJ09B0353-0300 Section 15 ROM On-Chip RAM Area Divisions in Boot Mode In boot mode, the RAM area is divided into an area used by the boot program and an area to which the user program is transferred via the SCI, as shown in figure 15.8. The boot program area can be used when a transition is made to the execution state for the user program transferred to RAM. H'FEF10 Boot program area (Approximately 1kbyte) H'FF300 User program transfer area (Approximately 3.0 kbytes) H'FFF0F Notes: 1. The boot program area cannot be used until a transition is made to the execution state for the user program transferred to RAM. Note also that the boot program remains in this RAM area even after control branches to the user program. 2. When flash memory emulation is performed using RAM, part of the user program transfer area (H'FF800 to H'FFBFF) is used as an area for carrying out emulation, and therefore user program transfer must not be performed to this area. Figure 15.8 RAM Areas in Boot Mode Notes on using the boot mode (1) When this LSI comes out of reset in boot mode, it measures the low period the input at the SCI's RXD1 pin. The reset should end with RXD1 high. After the reset ends, it takes about 100 states for this LSI to get ready to measure the low period of the RXD1 input. (2) If any data has been written to the flash memory (if all data is not H'FF), all flash memory blocks are erased when this mode is executed. Therefore, boot mode should be used for initial on-board programming, or for forced recovery if the program to be activated in user program mode is accidentally erased and user program mode cannot be executed, for example. (3) Interrupts cannot be used during programming or erasing of flash memory. Rev.3.00 Mar. 26, 2007 Page 458 of 682 REJ09B0353-0300 Section 15 ROM (4) The RXD1 and TXD1 pins should be pulled up on the board. (5) This LSI terminates transmit and receive operations by the on-chip SCI(channel 1) (by clearing the RE and TE bits in serial control register (SCR)) before branching to the user program. However, the adjusted bit rate is held in the bit rate register (BRR). At this time, the TXD1 pin is in the high level output state (P9DDR P91DDR=1, P9DR P91DR=1). Before branching to the user program the value of the general registers in the CPU are also undefined. Therefore, the general registers must be initialized immediately after control branches to the user program. Since the stack pointer (SP) is implicitly used during subroutine call, etc., a stack area must be specified for use by the user program. There are no other internal I/O registers in which the initial value is changed. (6) Transition to the boot mode executes a reset-start of this LSI after setting the MD0 to MD2 and FWE pins according to the mode setting conditions shown in table 15.6. At this time, this LSI latches the status of the mode pin inside the microcomputer to maintain 1 the boot mode status at the reset clear (startup with Low High) timing* . To clear boot mode, it is necessary to drive the FWE pin low during the reset, and then execute 1 reset release* . The following points must be noted: (a) Before making a transition from the boot mode to the regular mode, the microcomputer boot mode must be reset by reset input via the RES pin. At this time, the RES pin must be 3 hold at low level for at least 20 system clock.* (b) Do not change the input levels at the mode pins (MD2 to MD0) or the FWE pin while in boot mode. When making a mode transition, first enter the reset state by inputting a low level to the RES pin. When a watchdog timer reset was generated in the boot mode, the microcomputer mode is not reset and the on-chip boot program is restarted regardless of the state of the mode pin. (c) Do not input low level to the FWE pin while the boot program is executing and when 2 programming/erasing flash memory.* (7) If the mode pin and FWE pin input levels are changed from 0 V to VCC or from VCC to 0V during a reset (while a low level is being input to the RES pin), the microcomputer's operating mode will change. Therefore, since the state of the address dual port and bus control output signals (AS, RD, WR) changes, use of these pins as output signals during reset must be disabled outside the microcomputer. Notes: 1. The mode pin and FWE pin input must satisfy the mode programming setup time (tMDS) relative to the reset clear timing. 2. For notes on FWE pin High/Low, see section 15.9, Notes on Flash Memory Programming/Erasing. Rev.3.00 Mar. 26, 2007 Page 459 of 682 REJ09B0353-0300 Section 15 ROM 3. See section 4.2.2, Reset Sequence and 15.9, Notes on Flash Memory Programming/Erasing. With the mask ROM version of the H8/3039, H8/3038, H8/3037, and H8/3036, the minimum reset period during operation is 10 system clocks. However, the flash memory versions of the H8/3039 requires a minimum of 20 system clocks. 15.4.2 User Program Mode When set to the user program mode, this LSI can erase and program its flash memory by executing a user program. Therefore, on-chip flash memory on-board programming can be performed by providing a means of controlling FWE and supplying the write data on the board and providing a write program in a part of the program area. To select this mode, set the LSI to on-chip ROM enable modes 5 and 7 and apply a high level to the FWE pin. In this mode, the peripheral functions, other than flash memory, are performed the same as in modes 5 and 7. Since the flash memory cannot be read while it is being programmed/erased, place a programming program on external memory, or transfer the programming program to RAM area, and execute it in the RAM. In mode 6, do not program/erase the flash memory. When setting mode 6, always input low level to the FWE pin. Figure 15.9 shows the procedure for executing when transferred to on-chip RAM. During reset start, starting from the user program mode is possible. Rev.3.00 Mar. 26, 2007 Page 460 of 682 REJ09B0353-0300 Section 15 ROM 1 MD2 - MD0 = 101, 111 2 Reset start 2 3 Transfer on-board programming program to RAM. 3 4 4 Branch to program in RAM. 5 6 5 FWE = high (user program mode) 7 6 Execute on-board programming program in RAM (flash memory reprogramming). 8 7 Input low level to FWE after SWE bit clear (user program mode exit) Note: * For notes on FWE pin High/Low, see section 15.9, Notes on Flash Memory Programming/Erasing. 8 Execute user application program in flash memory. Figure 15.9 User Program Mode Execution Procedure (Example) Note: Normally do not apply a high level to the FWE pin. To prevent erroneous programming or erasing in the event of program runaway, etc., apply a high level to the FWE pin only when programming/erasing flash memory (including flash memory emulation by RAM). If program runaway, etc. causes overprogramming or overerasing of flash memory, the memory cells will not operate normally. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc. In mode 6, do not reprogram flash memory. When setting mode 6, always set the FWE pin to a low level. Rev.3.00 Mar. 26, 2007 Page 461 of 682 REJ09B0353-0300 Section 15 ROM 15.5 Programming/Erasing Flash Memory A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR. For a description of state transition by FLMCR bit setting, see figure 15.10. The flash memory cannot be read while being programmed or erased. Therefore, the program that controls flash memory programming/erasing (the programming control program) should be located and executed in on-chip RAM or external memory. For the programming/erasing notes, see section 15.9, Notes on Flash Memory Programming/Erasing. For the wait time after each bit in FLMCR is set or cleared, see section 18.2.5, Flash Memory Characteristics. Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR is executed by a program in flash memory. 2. When programming or erasing, set the FWE pin input level to the high level, and set FWE to 1. (programming/erasing will not be executed if FWE = 0). Rev.3.00 Mar. 26, 2007 Page 462 of 682 REJ09B0353-0300 Section 15 ROM *2 Erase setup state E=1 Erase mode E=0 ES *1 Normal mode FWE = 1 FWE = 0 U ES U = 0 1 =0 *3 Erase-verify mode On-board SWE = 1 Software programming mode reprogramming software reprogramming disable state SWE = 0 enable state = EV EV PSU =1 PSU = 1 P=1 Program setup state P=0 Programming mode PV PV = 0 =0 = 1 Program-verify mode Notes: : Normal mode : On-board programming mode 1. Do not make a state transition by setting or clearing two or more bits at the same time. 2. After transition from the erase mode to the erase setup state, do not make a transition to the erase mode without going through the software reprogramming enable state. 3. After transition from the programming mode to the program setup state, do not switch to the programming mode without going through the software reprogramming enable state. Figure 15.10 State Transition by Setting of Each Bit of FLMCR 15.5.1 Program Mode Follow the procedure shown in the program/program-verify flowchart in figure 15.11 to write data or programs to flash memory. Performing program operations according to this flowchart will enable data or programs to be written to flash memory without subjecting the device to voltage stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a time. For the wait time (x, y, z, , , , , ) after setting or clearing each bit in the flash memory control register (FLMCR) and the maximum programming count (N), see table 18.15. Following the elapse of (x) s or more after the SWE bit is set to 1 in flash memory control register (FLMCR), 32-byte program data is stored in the program data area and reprogram data area, and the 32-byte data in the reprogram data area written consecutively to the write addresses. (The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0.) 32 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. Rev.3.00 Mar. 26, 2007 Page 463 of 682 REJ09B0353-0300 Section 15 ROM Next, the watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc. Set a value greater than (y + z + + ) s as the WDT overflow period. Preparation for entering program mode (program setup) is performed next by setting the PSU bit in FLMCR. The operating mode is then switched to program mode by setting the P bit in FLMCR after the elapse of at least (y) s. The time while the P bit is set is the flash memory programming time. Make a program setting so that the time for one programming operation is within the range of (z) s. The wait time after P bit setting must be changed according to the number of reprogramming loops. For details, see section 18.2.5, Flash Memory Characteristics. 15.5.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory. Clear the P bit in FLMCR, then wait for at least () s before clearing the PSU bit to exit program mode. After exiting program mode, the watchdog timer setting is also cleared. Then the operating mode is switched to program-verify mode by setting the PV bit in FLMCR. Before reading in program-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. Next, the originally written data is compared with the verify data, and reprogram data is computed (see figure 15.11) and transferred to RAM. After verification of 32 bytes of data has been completed, exit programverify mode, wait for at least () s, then determine whether 32-byte programming has finished. If reprogramming is necessary, set program mode again, and repeat the program/program-verify sequence as before. However, ensure that the program/program-verify sequence is not repeated more than (N) times on the same bits. Note: A 32-byte area to store program data and a 32-byte area to store reprogram data are required in RAM. Rev.3.00 Mar. 26, 2007 Page 464 of 682 REJ09B0353-0300 Section 15 ROM Start *1 Set SWE bit in FLMCR Wait (x) s Store 32-byte write data in write data area and reprogram data area Programming operation counter n 1 Consecutively write 32-byte data in reprogram data area in RAM to flash memory Enable WDT Set PSU bit in FLMCR Wait (y) s Set P bit in FLMCR Wait (z) s Clear P bit in FLMCR Wait () s Clear PSU bit in FLMCR Wait () s Disable WDT Set PV bit in FLMCR Wait () s Set verify start address Programming end flag 0 *6 *2 *6 Start of programming *6 *7 End of programming *6 *6 *6 Notes: 1. Programming should be performed in the erased state. (Perform 32-byte programming on memory after all 32 bytes have been erased.) 2. Data transfer is performed by byte transfer (word transfer is not possible), with the write start address at a 32-byte boundary. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80, H'A0, H'C0, or H'E0. A 32-byte data transfer must be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the extra addresses. 3. Verify data is read in 16-bit (word) units. (Byte-unit reading is also possible.) 4. Reprogram data is determined by the computation shown in the table below (comparison of data stored in the program data area with verify data). Programming of reprogram data 0 bits is executed in the next programming loop. Therefore, even bits for which programming has been completed will be programmed again if the result of the subsequent verify operation is NG. 5. An area for storing write data (32 bytes) and an area for storing reprogram data (32 bytes) must be provided in RAM. The contents of the latter are rewritten in accordance with the reprogramming data computation. 6. The values of x, y, z, , , , , , and N are shown in section 18.2.5, Flash Memory Characteristics. 7. The value of z depends on the number of reprogramming loops (n). Details are given in section 18.2.5, Flash Memory Characteristics. H'FF dummy write to verify address Wait () s Read verify data *6 Write Data 0 0 Verify Data 0 1 0 1 Reprogram Data 1 0 1 1 *3 Comments Programming completed Programming incomplete; reprogram -- Still in erased state; no action Programming OK? OK Reprogram data computation NG Programming end flag 1 (unfinished) 1 1 *4 *5 RAM Transfer computation result to reprogram data area Increment verify address Program data storage area (32 bytes) No 32-byte data verification completed? Yes Clear PV bit in FLMCR Wait () s *6 Reprogram Programming end flag = 0? Yes Yes Clear SWE bit in FLMCR End of programming Clear SWE bit in FLMCR Programming failure No nn+1 *6 n > N? No Reprogram data storage area (32 bytes) Figure 15.11 Program/Program-Verify Flowchart Rev.3.00 Mar. 26, 2007 Page 465 of 682 REJ09B0353-0300 Section 15 ROM 15.5.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 15.12. For the wait time (x, y, z, , , , , ) after setting or clearing of each bit in the flash memory control register (FLMCR) and the maximum erase count (N), see table 18.15. To erase the contents of flash memory, make a 1 bit setting for the flash memory area to be erased in erase block register (EBR) at least (x) s after setting the SWE bit to 1 in FLMCR. Next, the watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. Set a value greater than (z) ms + (y + + ) s as the WDT overflow period. Preparation for entering erase mode (erase setup) is performed next by setting the ESU bit in FLMCR. The operating mode is then switched to erase mode by setting the E bit in FLMCR after the elapse of at least (y) s. The time during which the E bit is set is the flash memory erase time. Ensure that the erase time does not exceed (z) ms. Note: With flash memory erasing, preprogramming (setting all data in the memory to be erased to "0") is not necessary before starting the erase procedure. 15.5.4 Erase-Verify Mode In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased. After the elapse of the fixed erase time, clear the E bit in FLMCR, then wait for at least () s before clearing the ESU bit to exit erase mode. After exiting erase mode, the watchdog timer setting is also cleared. The operating mode is then switched to erase-verify mode by setting the EV bit in FLMCR. Before reading in erase-verify mode, a dummy write of H'FF data should be made to the addresses to be read. The dummy write should be executed after the elapse of () s or more. When the flash memory is read in this state (verify data is read in 16-bit units), the data at the latched address is read. Wait at least () s after the dummy write before performing this read operation. If the read data has been erased (all "1"), a dummy write is performed to the next address, and erase-verify is performed. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as before. However, do not repeat the erase/erase-verify sequence more than (N) times. Rev.3.00 Mar. 26, 2007 Page 466 of 682 REJ09B0353-0300 Section 15 ROM Start *1 *2 Set SWE bit in FLMCR Wait (x) s Erase counter n 1 Set EBR Enable WDT Set ESU bit in FLMCR Wait (y) s Set E bit in FLMCR Wait (z) ms Clear E bit in FLMCR Wait () s Clear ESU bit in FLMCR Wait () s Disable WDT Set EV bit in FLMCR Wait () s Set block start address to verify address H'FF dummy write to verify address Wait () s Read verify data Increment verify address *4 *5 *2 Start of erase *2 End of erase *2 *2 *2 *2 *3 No Verify data = H'FFFF? YES No Last address of block? Yes Clear EV bit in FLMCR Wait () s Re-erase nn+1 *2 Clear EV bit in FLMCR Wait () s *2 n > N? Yes No *2 Clear SWE bit in FLMCR End of erasing Notes: 1. 2. 3. 4. 5. Clear SWE bit in FLMCR Erase failure Preprogramming (setting erase block data to all 0s) is not necessary. The values of x, y, z, , , , , , and N are shown in section 18.2.5, Flash Memory Characteristics. Verify data is read in 16-bit (word) units. (Byte-unit reading is also possible.) Set only one bit in EBR two or more bits must not be set simultaneously. Erasing is performed in block units. To erase multiple blocks, each block must be erased in turn. Figure 15.12 Erase/Erase-Verify Flowchart (Single-Block Erasing) Rev.3.00 Mar. 26, 2007 Page 467 of 682 REJ09B0353-0300 Section 15 ROM 15.6 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 15.6.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Hardware protection is reset by settings in the flash memory control register (FLMCR) and erase block register (EBR). In the case of error protection, the P bit and E bit can be set, but a transition is not made to program mode or erase mode. (See table 15.8.) Rev.3.00 Mar. 26, 2007 Page 468 of 682 REJ09B0353-0300 Section 15 ROM Table 15.8 Hardware Protection Function Item FWE pin protection Description * When a low level is input to the FWE pin, FLMCR and EBR are initialized, and the program/erase-protected state 4 is entered.* In a reset (including a WDT overflow reset) and in standby mode, FLMCR and EBR are initialized, and the program/erase-protected state is entered. In a reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation stabilizes after powering on (The minimum oscillation stabilization time is 20ms). In the case of a reset during operation, hold the RES pin low for at least 20 5 system clock cycles.* When a microcomputer operation error (error generation (FLER=1)) was detected while flash memory was being programmed/erased, error protection is enabled. At this time, the FLMCR and EBR settings are held, but programming/erasing is aborted at the time the error was generated. Error protection is released only by a reset via the RES pin or a WDT reset, or in the hardware standby mode. No No* 3 Program Erase No* 2 Verify* No 1 No* 3 Reset/standby protection * No No* 3 No * Error protection * Yes Notes: 1. 2. 3. 4. 5. Two modes: program-verify and erase-verify. The RAM area that overlapped flash memory is deleted. All blocks become unerasable and specification by block is impossible. For more information, see section 15.9, Notes on Flash Memory Programming/Erasing. See sections 4.2.2, Reset Sequence and 15.9, Notes on Flash Memory Programming/Erasing. This LSI requires a minimum reset time during operation of 20 system clocks. Rev.3.00 Mar. 26, 2007 Page 469 of 682 REJ09B0353-0300 Section 15 ROM 15.6.2 Software Protection Software protection can be implemented by setting the RAMS bit in RAM control register (RAMCR) and erase block register (EBR). When software protection is in effect, setting the P or E bit in flash memory control register (FLMCR) does not cause a transition to program mode or erase mode. (See table 15.9.) Table 15.9 Software Protection Function Item Emulation 2 protection* Block specification protection Description Setting the RAMS bit in RAMCR sets the program/erase-protected state for all blocks. Erase protection can be set for individual blocks by settings in erase block register 4 (EBR).* However, program protection is disabled. Setting EBR to H'00 places all blocks in the erase-protected state. Notes: 1. 2. 3. 4. Two modes: program-verify mode and erase-verify mode. Programming to the RAM area that overlaps flash memory is possible. All blocks become unerasable, and specification by block is impossible. Set H'00 in the EBR bits, except for erase. Program Erase No* 2 Verify* Yes 1 No* 3 -- No Yes Rev.3.00 Mar. 26, 2007 Page 470 of 682 REJ09B0353-0300 Section 15 ROM 15.6.3 Error Protection In error protection, an error is detected when this LSI runaway occurs during flash memory programming/erasing*1, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing. If the LSI malfunctions during flash memory programming/erasing, the FLER bit*2 is set to 1 in flash memory status register (FLMSR) and the error protection state is entered. The FLMCR and EBR settings*3 are retained, but program mode or erase mode is aborted at the point at which the error occurred. When 1 is set in the FLER bit, transition to the program mode or erase mode cannot be made even by setting the P and E bits in FLMCR. However, PV and EV bit in FLMCR setting is enabled, and a transition can be made to verify mode. Error protection is released only by a reset via the RES pin or a WDT reset, or in the hardware standby mode. Figure 15.13 shows the flash memory state transition diagram. Notes: 1. This is the state in which the P or E bit in FLMCR is set to 1. In this state, NMI input is disabled. For more information, see section 15.6.4, NMI Input Disable Conditions. 2. For a detailed description of the FLER bits setting conditions, see section 15.3.4, Flash Memory Status Register (FLMSR). 3. Data can be written to FLMCR and EBR. However, when transition to the software standby mode was made in the error protection state, the registers are initialized. Rev.3.00 Mar. 26, 2007 Page 471 of 682 REJ09B0353-0300 Section 15 ROM Re set or , hard sof Re twa ware set s re sta tand RD VF PR ER FLER = 0 mo relea nd by de se, by m mo ode sta relea hard P=1 or E=1 de , nd se, wa by mo and re sta P = 0 and E = 0 de sof n rel twa dby ea se re Reset or standby mode Program mode (hardware protection) Erase mode Reset or hardware standby mode Memory read verify mode RD VF PR ER FLER = 0 (so Er ro ftw Error occurrence ro cc ar urre es n tan ce db ym o are rdw a r h ode to se by m Re and st RD VF PR ER INIT FLER = 0 de ) Reset or hardware standby mode Error protection mode RD VF PR ER FLER = 1 Software standby mode Software standby mode release Error protection mode (software standby mode) RD VF PR ER INIT FLER = 1 Legend: RD: Memory read enable VF: Verify-read enable PR: Programming enable ER: Erasing enable RD: Memory read disabled VF: Verify-read disabled PR: Programming disabled ER: Erasing disabled INIT: Registers (FLMCR, EBR) initialize state Figure 15.13 Flash Memory State Transitions (When High Level Apply to FWE Pin in Modes 5 and 7 (On-Chip ROM Enabled)) The error protection function is disabled for errors other than the FLER bit set conditions. If considerable time elapses up to transit to this protection state, the flash memory may already be damaged. As a result, this function cannot completely protect the flash memory against damage. Therefore, to prevent such erroneous operation, operation must be carried out correctly in according with the program/erase algorithms in the state that flash write enable (FWE) is set. In addition, the operation must be always carried out correctly by supervising microcomputer errors inside and outside the chip with the watchdog timer, etc. At transition to this protection mode, the flash memory may be erroneously programmed or erased, or its abort may result in incomplete Rev.3.00 Mar. 26, 2007 Page 472 of 682 REJ09B0353-0300 Section 15 ROM programming and erasing. In such cases, always forcibly return (reprogram) by boot mode. However, overprogramming and overerasing may prevent the boot mode from starting normally. 15.6.4 NMI Input Disable Conditions While flash memory is being programmed/erased and the boot program is executing in the boot 1 mode (however, period up to branching to on-chip RAM area)* , NMI input is disabled because the programming/erasing operations have priority. This is done to avoid the following operation states: 1. Generation of an NMI input during programming/erasing violates the program/erase algorithms and normal operation can not longer be assured. 2. Vector-read cannot be carried out normally* during NMI exception handling during programming/erasing and the microcomputer runs away as a result. 3. If an NMI input is generated during boot program execution, the normal boot mode sequence cannot be executed. Therefore, this LSI has conditions that exceptionally disable NMI inputs only in the on-board programming mode. However, this does not assure normal programming/erasing and microcomputer operation. Thus, in the FWE application state, all requests, including NMI, inside and outside the microcomputer, exception handling, and bus release must be restricted. NMI inputs are also disabled in the error protection state and the state that holds the P or E bit in FLMCR during flash memory emulation by RAM. Notes: 1. Indicates the period up to branching to the on-chip RAM boot program area (H'FEF10 to H'FF2FF). (This branch occurs immediately after user program transfer was completed.) Therefore, after branching to RAM area, NMI input is enabled in states other than the program/erase state. Thus, interrupt requests inside and outside the microcomputer must be disabled until initial writing by user program (writing of vector table and NMI processing program, etc.) is completed. 2. In this case, vector read is not performed normally for the following two reasons: a. The correct value cannot be read even by reading the flash memory during programming/erasing. (Value is undefined.) b. If a value has not yet been written to the NMI vector table, NMI exception handling will not be performed correctly. 2 Rev.3.00 Mar. 26, 2007 Page 473 of 682 REJ09B0353-0300 Section 15 ROM 15.7 Flash Memory Emulation by RAM Erasing and programming the flash memory takes time, which can make it difficult to tune parameters and other data in real time. In this case, overlapping part (H'FF800 to H'FFBFF) of RAM onto a small block area of flash memory can be performed to emulate real-time reprogramming of flash memory. This RAM reassignment is performed using bits 3 to 1 in the RAM control register (RAMCR). After the RAM area change, two areas can be accessed: the overlapped flash memory area and the original RAM area (H'FF800 to H'FFBFF). For a description of the RAMCR and RAM area setting procedure, see section 15.3.3, RAM Control Register (RAMCR). Example of real-time emulation of flash memory An example of RAM area H'FF800 to H'FFBFF overlapping EB2 (H'00800 to H'00BFF) flash memory area is shown below. Procedure: 1. Part (H'FF800 to H'FFBFF) of RAM overlaps the area (EB2) needed to carry out real-time reprogramming. (Bits 3 to 1 in the RAMCR are set to 1, 1, 0 and the overlap flash memory area (EB2) is selected.) Overlapping RAM EB2 H'00800 area H'00BFF 2. Real-time reprogramming is carried out using the overlapping RAM. 3. After the reprogramming data is verified, RAM overlapping is released. (RAMS bits are cleared.) 4. The data written to H'FF800 to H'FFBFF in RAM are written to flash memory space. On-chip RAM area Note: * When part (H'FF800 to H'FFBFF) of RAM overlapped a small block area of flash memory, the overlapped flash memory area cannot be accessed. This area can be accessed by releasing overlapping. H'00000 Block area Flash memory space * H'FEF10 (Image RAM area) H'00FFF H'FF800 H'FFBFF H'FFC00 H'FFF0F (Real RAM area) Figure 15.14 Example of RAM Overlapping Operation Rev.3.00 Mar. 26, 2007 Page 474 of 682 REJ09B0353-0300 Section 15 ROM Notes on use of the RAM emulation function (1) Notes on flash write enable (FWE) high/low Care is necessary to prevent erroneous programming/erasing at FWE = high/low, the same as in the on-board programming mode. To prevent erroneous programming and erasing due to program runaway, etc., during FWE application, in particular, the watchdog timer should be set when the P, or E bit is set to 1 in FLMCR, even while the emulation function is being used. For more information, see section 15.9, Notes on Flash Memory Programming/Erasing. (2) NMI input disable conditions When the P and E bits in FLMCR are set, NMI input is disabled, the same as normal program/erase even when using the emulation function. NMI input is cleared when the P and E bits are reset (including watchdog timer reset), in the standby mode, when a high level is not applied to FWE, and when the SWE bit in FLMCR is 0 in state in which a high level is input to FWE. 15.8 15.8.1 Flash Memory PROM Mode PROM Mode Setting This LSI has a PROM mode, besides an on-board programming mode, as a flash memory program/erase mode. In the PROM mode, a program can be freely written to the on-chip ROM using a PROM programmer that supports the Renesas Technology 128 kbytes flash memory onchip microcomputer device type. For notes on PROM mode use, see sections 15.8.9, Notes on Memory Programming and 15.9, Notes on Flash Memory Programming/Erasing. Rev.3.00 Mar. 26, 2007 Page 475 of 682 REJ09B0353-0300 Section 15 ROM 15.8.2 Memory Map Figure 15.15 shows the PROM mode memory map. Address in MCU mode H'00000 Address in PROM mode H'00000 This LSI On-chip ROM area H'1FFFF H'1FFFF Figure 15.15 PROM Mode Memory Map 15.8.3 PROM Mode Operation Table 15.10 shows how the different operating modes are set when using PROM mode, and table 15.11 lists the commands used in PROM mode. Details of each mode are given below. * Memory Read Mode Memory read mode supports byte reads. * Auto-Program Mode Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. * Auto-Erase Mode Auto-erase mode supports automatic erasing of the entire flash memory. Status polling is used to confirm the end of auto-erasing. * Status Read Mode Status polling is used for auto-programming and auto-erasing, and normal termination can be confirmed by reading the I/O 6 signal. In status read mode, error information is output if an error occurs. Rev.3.00 Mar. 26, 2007 Page 476 of 682 REJ09B0353-0300 Section 15 ROM Table 15.10 Settings for Each Operating Mode in PROM Mode Pin Names* Mode Read Output disable Command write Chip disable* 1 3 FWE VCC or 0 VCC or 0 VCC or 0 VCC or 0 CE L L L H OE L H H X WE H H L X D0 to D7 Data output Hi-Z Data input Hi-Z A0 to A17 Ain X Ain* X 2 Legend: L: Low level H: High level X: Undefined Hi-Z: High impedance Notes: For command writes when making a transition to auto-program or auto-erase mode, input Vcc (V) to FWE. 1. Chip disable is not a standby state; internally, it is an operation state. 2. Ain indicates that there is also address input in auto-program mode. 3. The pin names are those assigned in this LSI PROM mode. Table 15.11 PROM Mode Commands Number of Cycles 1 129 2 2 1st Cycle Mode Write Write Write Write Address X X X X Data H'00 H'40 H'20 H'71 Mode Read Write Write Write 2nd Cycle Address RA WA X X Data Dout Din H'20 H'71 Command Name Memory read mode Auto-program mode Auto-erase mode Status read mode Legend: RA: Read address WA: Program address Dout: Read data Din: Program data Note: In auto-program mode, 129 cycles are required for command writing by a simultaneous 128-byte write. Rev.3.00 Mar. 26, 2007 Page 477 of 682 REJ09B0353-0300 Section 15 ROM Table 15.12 DC Characteristics in Memory Read Mode Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C Item Input high voltage Input low voltage 07-00, A16-A0 07-00, A16-A0 Symbol VIH VIL VT VT - + + - Min 2.2 0.3 1.0 2.0 0.4 2.4 -- -- -- -- -- Typ -- -- -- -- -- -- -- -- 40 50 50 Max Vcc +0.3 0.8 2.5 3.5 -- -- 0.45 2 65 85 85 Unit V V V V V V V A mA mA mA Test Conditions Schmitt trigger OE, CE, WE input voltage VT - VT Output high voltage Output low voltage Input leakage current VCC current 07-00 07-00 07-00, A16-A0 Reading VOH VOL | ILI | Icc Icc IOH = -200 A IOL = 1.6 mA Programming Icc Erasing Note: For the electrical characteristics of the flash memory version, see section 18.2.1, Absolute Maximum Ratings. Exceeding the absolute maximum ratings may cause permanent damage to the chip. Rev.3.00 Mar. 26, 2007 Page 478 of 682 REJ09B0353-0300 Section 15 ROM 15.8.4 Memory Read Mode AC Characteristics Table 15.13 AC Characteristics in Memory Read Mode Transition Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Notes Command write A16-A0 tces CE OE WE tds I/O7-I/O0 tdh twep tceh tnxtc Memory read mode Address stable tf tr Note: Data is latched on the rising edge of WE. Figure 15.16 Timing Waveform in Memory Read Mode Transition Rev.3.00 Mar. 26, 2007 Page 479 of 682 REJ09B0353-0300 Section 15 ROM Table 15.14 AC Characteristics in Memory Contents Read Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C Item Access time CE output delay time OE output delay time Output disable delay time Data output hold time Symbol tacc tce toe tdf toh Min -- -- -- -- 5 Max 20 150 150 100 -- Unit s ns ns ns ns Notes A16-A0 Address stable Address stable CE OE WE VIL VIL VIH tacc toh tacc toh I/O7-I/O0 Figure 15.17 CE OE Enable State Read CE/OE A16-A0 Address stable tce Address stable tce CE OE WE I/O7-I/O0 VIH tacc toe toe tacc toh tdf toh tdf Figure 15.18 CE OE Clock Read CE/OE Rev.3.00 Mar. 26, 2007 Page 480 of 682 REJ09B0353-0300 Section 15 ROM Table 15.15 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep tr tf Min 20 0 0 50 50 70 -- -- Max -- -- -- -- -- -- 30 30 Unit s ns ns ns ns ns ns ns Notes Memory read mode A16-A0 Address stable tnxtc CE OE WE Another mode command write tces tceh tf twep tr tds I/O7-I/O0 tdh Note: Do not enable WE and OE simultaneously. Figure 15.19 Transition From Memory Read Mode to Another Mode Rev.3.00 Mar. 26, 2007 Page 481 of 682 REJ09B0353-0300 Section 15 ROM 15.8.5 Auto-Program Mode AC Characteristics Table 15.16 AC Characteristics in Auto-Program Mode Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Address setup time Address hold time Memory write time WE rise time WE fall time Write setup time Write end setup time Symbol tnxtc tceh tces tdh tds twep twsts tspa tas tah twrite tr tf tpns tpnh Min 20 0 0 50 50 70 1 -- 0 60 1 -- -- 100 100 Max -- -- -- -- -- -- -- 150 -- -- 3000 30 30 -- -- Unit s ns ns ns ns ns ms ns ns ns ms ns ns ns ns Notes Rev.3.00 Mar. 26, 2007 Page 482 of 682 REJ09B0353-0300 Section 15 ROM FWE A16-A0 Address stable tpnh tpns CE OE WE tces tceh tnxtc tnxtc tf twep tr tdh tas tah Data transfer 1byte to 128bytes twsts tspa twrite Programming operation end identification signal tds I/O7 I/O6 Programming normal end identification signal I/O5-I/O0 H'40 H'00 Figure 15.20 Auto-Program Mode Timing Waveforms Cautions on Use of Auto-Program Mode * In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. * A 128-byte data transfer is necessary even when programming fewer than 128 bytes. In this case, H'FF data must be written to the extra addresses. * If a value other than an effective address is input, processing will switch to a memory write operation but a write error will be flagged. * Memory address transfer is performed in the second cycle (figure 15.20). Do not perform transfer after the second cycle. * Do not perform a command write during a programming operation. * Perform one auto-programming operation for a 128-byte block for each address. Characteristics are not guaranteed for two or more programming operations. * Confirm normal end of auto-programming by checking I/O 6. Alternatively, status read mode can also be used for this purpose. Rev.3.00 Mar. 26, 2007 Page 483 of 682 REJ09B0353-0300 Section 15 ROM 15.8.6 Auto-Erase Mode AC Characteristics Table 15.17 AC Characteristics in Auto-Erase Mode Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width Status polling start time Status polling access time Memory erase time WE rise time WE fall time Erase setup time Erase end setup time Symbol tnxtc tceh tces tdh tds twep tests tspa terase tr tf tens tenh Min 20 0 0 50 50 70 1 -- 100 -- -- 100 100 Max -- -- -- -- -- -- -- 150 40000 30 30 -- -- Unit s ns ns ns ns ns ms ns ms ns ns ns ns Notes FWE A16-A0 tenh tens CE OE tces tceh tnxtc tnxtc tf WE twep tr tests tspa tds I/O7 tdh terase Erase end identification signal I/O6 Erase normal and confirmation signal I/O5-I/O0 H'20 H'20 H'00 Figure 15.21 Auto-Erase Mode Timing Waveforms Rev.3.00 Mar. 26, 2007 Page 484 of 682 REJ09B0353-0300 Section 15 ROM Caution on Use of Erase-Program Mode * Auto-erase mode supports only entire memory erasing. * Do not perform a command write during auto-erasing. * Confirm normal end of auto-erasing by checking I/O 6. Alternatively, status read mode can also be used for this purpose. 15.8.7 Status Read Mode AC Characteristics Table 15.18 AC Characteristics in Status Read Mode Conditions: VCC = 5.0 V 10%, VSS = 0 V, Ta = 25C 5C Item Command write cycle CE hold time CE setup time Data hold time Data setup time Write pulse width OE output delay time Disable delay time CE output delay time WE rise time WE fall time Symbol tnxtc tceh tces tdh tds twep toe tdf tce tr tf Min 20 0 0 50 50 70 -- -- -- -- -- Max -- -- -- -- -- -- 150 100 150 30 30 Unit s ns ns ns ns ns ns ns ns ns ns Notes Rev.3.00 Mar. 26, 2007 Page 485 of 682 REJ09B0353-0300 Section 15 ROM A16-A0 tces CE tceh tnxtc tces tceh tnxtc tce tnxtc OE tf WE twep tr tf twep tr toe tdf tds I/O7-I/O0 H'71 tdh tds H'71 tdh Note: I/O3 and I/O2 are undefined. Figure 15.22 Status Read Mode Timing Waveforms Table 15.19 Status Read Mode Return Commands Pin Name Attribute I/O7 I/O6 I/O5 Programming error I/O4 Erase error I/O3 -- I/O2 -- I/O1 I/O0 Normal Command end error identification 0 Normal end: 0 Abnormal end: 1 0 Command error: 1 Otherwise: 0 ProgramEffective ming or address erase count error exceeded 0 Count exceeded: 1 Otherwise: 0 0 Effective address error: 1 Otherwise: 0 Initial value Indications 0 Programming error: 1 Otherwise: 0 0 Erase error: 1 Otherwise: 0 0 -- 0 -- Notes on status read mode After exiting auto-program mode or auto-erase mode, status read mode must be executed without dropping the power supply. Immediately after powering on, or once powering off, the return command is undefined. Rev.3.00 Mar. 26, 2007 Page 486 of 682 REJ09B0353-0300 Section 15 ROM 15.8.8 PROM Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Table 15.20 Stipulated Transition Times to Command Wait State Item Standby release (oscillation settling time) PROM mode setup time VCC hold time Symbol tosc1 tbmv tdwn Min 20 10 0 Max -- -- -- Unit ms ms ms Notes tosc1 VCC RES FWE tbmv Memory read mode Command wait state Auto-program mode Auto-erase mode Command wait state Normal/abnormal end identification t dwn Note: Set the FWE input pin low level, except in the auto-program and auto-erase modes. Figure 15.23 Oscillation Stabilization Time, Boot Program Transfer Time Rev.3.00 Mar. 26, 2007 Page 487 of 682 REJ09B0353-0300 Section 15 ROM 15.8.9 Notes on Memory Programming * When programming addresses which have previously been programmed, carry out autoerasing before auto-programming (figure 15.24). * When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas. For other chips for which the erasure history is unknown, it is recommended that autoerasing be executed to check and supplement the initialization (erase) level. 2. In the PROM mode, auto-programming to a 128-byte programming unit block should be performed only once. Do not perform additional programming to a programmed 128-byte programming unit block. To reprogram, perform auto-programming after auto-erasing. Reprogram to programmed address Auto-erase (chip batch) Auto-program End Figure 15.24 Reprogramming to Programmed Address 15.9 Notes on Flash Memory Programming/Erasing The following describes notes when using the on-board programming mode, RAM emulation function, and PROM mode. (1) Program/erase with the specified voltage and timing. Applied voltages in excess of the rating can permanently damage the device. Use a PROM writer that supports the Renesas Technology 128 kbytes flash memory on-board microcomputer device type. Do not set the PROM writer at the HN28F101. If the PROM writer is set to the HN28F101 by mistake, a high level can be input to the FWE pin and the LSI can be destroyed. Rev.3.00 Mar. 26, 2007 Page 488 of 682 REJ09B0353-0300 Section 15 ROM (2) Notes on powering on/powering off (See figures 15.25 to 15.27.) Input a high level to the FWE pin after verifying Vcc. Before turning off Vcc, set the FWE pin to a low level. When powering on and powering off the Vcc power supply, fix the FWE pin a low level and set the flash memory to the hardware protection mode. Be sure that the powering on and powering off timing is satisfied even when the power is turned off and back on in the event of a power interruption, etc. If this timing is not satisfied, microcomputer runaway, etc., may cause overprogramming or overerasing and the memory cells may not operate normally. (3) Notes on FWE pin High/Low switching (See figures 15.25 to 15.27.) Input FWE in the state microcomputer operation is verified. If the microcomputer does not satisfy the operation confirmation state, fix the FWE pin at a low level to set the protection mode. To prevent erroneous programming/erasing of flash memory, note the following in FWE pin High/Low switching: * Apply an input to the FWE pin after the Vcc voltage has stabilized within the rated voltage. If an input is applied to the FWE pin when the microcomputer Vcc voltage does not satisfy the rated voltage, flash memory may be erroneously programmed or erased because the microcomputer is in the unconfirmed state. * Apply an input to the FWE pin when the oscillation has stabilized (after the oscillation stabilization time). When turning on the Vcc power, apply an input to the FWE pin after holding the RES pin at a low level during the oscillation stabilization time (tosc1=20ms). Do not apply an input to the FWE pin when oscillation is stopped or unstable. * In the boot mode, perform FWE pin High/Low switching during reset. In transition to the boot mode, input FWE = High level and set MD2 to MD0 while the RES input is low. At this time, the FWE and MD2 to MD0 inputs must satisfy the mode programming setup time (tMDS) relative to the reset clear timing. The mode programming setup time is necessary for RES reset timing even in transition from the boot mode to another mode. In reset during operation, the RES pin must be held at a low level for at least 20 system clocks. * In the user program mode, FWE = High/Low switching is possible regardless of the RES input. FWE input switching is also possible during program execution on flash memory. Rev.3.00 Mar. 26, 2007 Page 489 of 682 REJ09B0353-0300 Section 15 ROM * Apply an input to FWE when the program is not running away. When applying an input to the FWE pin, the program execution state must be supervised using a watchdog timer, etc. * Input low level to the FWE pin when the SWE, ESU, PSU, EV, PV, E, and P bits in FLMCR have been cleared. Do not erroneously set the SWE, ESU, PSU, EV, PV, E, and P bits when FWE High/Low. (4) Do not input a constant high level to the FWE pin. To prevent erroneous programming/erasing in the event of program runaway, etc., input a high level to the FWE pin only when programming/erasing flash memory (including flash memory emulation by RAM). Avoid system configurations that constantly input a high level to the FWE pin. Handle program runaway, etc. by starting the watchdog timer so that flash memory is not overprogrammed/overerased even while a high level is input to the FWE pin. (5) Program/erase the flash memory in accordance with the recommended algorithms. The recommended algorithms can program/erase the flash memory without applying voltage stress to the device or sacrificing the reliability of the program data. When setting the PSU and ESU bits in FLMCR, set the watchdog timer for program runaway, etc. (6) Do not set/clear the SWE bit while a program is executing on flash memory. Before performing flash memory program execution or data read, clear the SWE bit. If the SWE bit is set, the flash data can be reprogrammed, but flash memory cannot be accessed for purposes other than verify (verify during programming/erase). Similarly perform flash memory program execution and data read after clearing the SWE bit even when using the RAM emulation function with a high level input to the FWE pin. However, RAM area that overlaps flash memory space can be read/programmed whether the SWE bit is set or cleared. (7) Do not use an interrupt during flash memory programming or erasing. Since programming/erase operations (including emulation by RAM) have priority when a high level is input to the FWE pin, disable all interrupt requests, including NMI. (8) Do not perform additional programming. Reprogram flash memory after erasing. With on-board programming, program to 32-byte programming unit blocks one time only. Program to 128-byte programming unit blocks one time only even in the PROM mode. Erase all the programming unit blocks before reprogramming. Bus release must also be disabled. Rev.3.00 Mar. 26, 2007 Page 490 of 682 REJ09B0353-0300 Section 15 ROM (9) Before programming, check that the chip is correctly mounted in the PROM programmer. Overcurrent damage to the device can result if the index marks on the PROM programmer socket, socket adapter, and chip are not correctly aligned. (10) Do not touch the socket adapter or chip during programming. Touching either of these can cause contact faults and write errors. Wait time: x Programming and erase possible tOSC1 VCC tMDS Min 0 s FWE Min 0 s MD2 to MD0*1 tMDS RES SWE set SWE clear SWE bit : Flash memory access disabled period (x: Wait time after SWE setting)*2 : Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1. Always fix the level by pulling down or pulling up the mode pins (MD2 to MD0) until powering off, except for mode switching. 2. See section 18.2.5, Flash Memory Characteristics. Figure 15.25 Powering On/Off Timing (Boot Mode) Rev.3.00 Mar. 26, 2007 Page 491 of 682 REJ09B0353-0300 Section 15 ROM Wait time: x Programming and erase possible tOSC1 VCC Min 0 s FWE MD2 to MD0*1 tMDS RES SWE set SWE clear SWE bit : Flash memory access disabled period (x: Wait time after SWE setting)*2 : Flash memory reprogrammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1. Always fix the level by pulling down or pulling up the mode pins (MD2 to MD0) except for mode switching. 2. See section 18.2.5, Flash Memory Characteristics. Figure 15.26 Powering On/Off Timing (User Program Mode) Rev.3.00 Mar. 26, 2007 Page 492 of 682 REJ09B0353-0300 Section 15 ROM Wait Programming and time: x erase possible Programming and Wait erase Wait Programming and time: x possible time: x erase possible Programming and Wait erase time: x possible tOSC1 VCC Min 0 s FWE tMDS MD2 to MD0 tMDS tRESW RES SWE set SWE clear tMDS*2 SWE bit Mode switching*1 Boot mode Mode User switching*1 mode User program mode User mode User program mode : Flash memory access disabled time (x: Wait time after SWE setting)*3 : Flash memory reprogammable period (Flash memory program execution and data read, other than verify, are disabled.) Notes: 1. In transition to the boot mode and transition from the boot mode to another mode, mode switching via RES input is necessary. During this switching period (period during which a low level is input to the RES pin), the state of the address dual port and bus control output signals (AS,RD,WR) changes. Therefore, do not use these pins as output signals during this switching period. 2. When making a transition from the boot mode to another mode, the mode programming setup time tMDS relative to the RES clear timing is necessary. 3. See section 18.2.5, Flash Memory Characteristics. Figure 15.27 Mode Transition Timing (Example: Boot Mode User Mode User Program Mode) Rev.3.00 Mar. 26, 2007 Page 493 of 682 REJ09B0353-0300 Section 15 ROM 15.10 Mask ROM Overview 15.10.1 Block Diagram Figure 15.28 shows a block diagram of the ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'00000 H'00002 H'00001 H'00003 On-chip ROM H'1FFFE Even addresses H'1FFFF Odd addresses Figure 15.28 ROM Block Diagram (H8/3039) Rev.3.00 Mar. 26, 2007 Page 494 of 682 REJ09B0353-0300 Section 15 ROM 15.11 Notes on Ordering Mask ROM Version Chip When ordering the H8/3039 Group chips with a mask ROM, note the following. * When ordering through an EPROM, use a 128-kbyte one. * Fill all the unused addresses with H'FF as shown in figure15.29 to make the ROM data size 128 kbytes for all H8/3039 Group chips, which incorporate different sizes of ROM. This applies to ordering through an EPROM and through electrical data transfer. * The flash memory versions only registers for flash memory control (FLMCR, EBR, RAMCR, and FLMSR) are not provided in the mask ROM versions. Reading the corresponding addresses in a mask ROM version will always return 1s, and writes to these addresses are disabled. This must be borne in mind when switching from the flash memory versions to a mask ROM version. HD6433039 (ROM: 128 kbytes) Address: H'00000-H'1FFFF H'00000 HD6433038 (ROM: 64 kbytes) Address: H'00000-H'0FFFF H'00000 HD6433037 (ROM: 32 kbytes) Address: H'00000-H'07FFF H'00000 HD6433036 (ROM: 16 kbytes) Address: H'00000-H'03FFF H'00000 H'03FFF H'04000 H'07FFF H'08000 H'0FFFF H'10000 Not used* Not used* Not used* H'1FFFF H'1FFFF H'1FFFF H'1FFFF Note: * Program H'FF to all addresses in these areas. Figure 15.29 Mask ROM Addresses and Data Rev.3.00 Mar. 26, 2007 Page 495 of 682 REJ09B0353-0300 Section 15 ROM Rev.3.00 Mar. 26, 2007 Page 496 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator Section 16 Clock Pulse Generator 16.1 Overview This LSI has a built-in clock pulse generator (CPG) that generates the system clock () and other internal clock signals (/2 to /4096). After duty adjustment, a frequency divider divides the clock 1 frequency to generate the system clock (). The system clock is output at the pin* and furnished as a master clock to prescalers that supply clock signals to the on-chip supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency divider by settings in a division control register (DIVCR). Power consumption in the chip is reduced in 2 almost direct proportion to the frequency division ratio* . Notes: 1. Usage of the pin differs depending on the chip operating mode and the PSTOP bit setting in the module standby control register (MSTCR). For details, see section 17.7, System Clock Output Disabling Function. 2. The division ratio of the frequency divider can be changed dynamically during operation. The clock output at the pin also changes when the division ratio is changed. The frequency output at the pin is shown below. = EXTAL x n EXTAL: Frequency of crystal resonator or external clock signal n: Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8) Rev.3.00 Mar. 26, 2007 Page 497 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator 16.1.1 Block Diagram Figure 16.1 shows a block diagram of the clock pulse generator. CPG XTAL Oscillator EXTAL Duty adjustment circuit Frequency divider Prescalers Division control register Data bus /2 to /4096 Figure 16.1 Block Diagram of Clock Pulse Generator 16.2 Oscillator Circuit Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock signal. Rev.3.00 Mar. 26, 2007 Page 498 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator 16.2.1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as in the example in figure 16.2. The damping resistance Rd should be selected according to table 16.1. An AT-cut parallel-resonance crystal should be used. C L1 EXTAL XTAL Rd C L2 C L1 = C L2 = 10 pF to 22 pF Figure 16.2 Connection of Crystal Resonator (Example) Table 16.1 Damping Resistance Value (Example) Frequency (MHz) Rd () 2 1k 4 500 8 200 10 0 12 0 16 0 18 0 Crystal Resonator Figure 16.3 shows an equivalent circuit of the crystal resonator. The crystal resonator should have the characteristics listed in table 16.2. CL L XTAL Rs EXTAL CO AT-cut parallel-resonance type Figure 16.3 Crystal Resonator Equivalent Circuit Rev.3.00 Mar. 26, 2007 Page 499 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator Table 16.2 Crystal Resonator Parameters Frequency (MHz) 2 Rs max () Co max (pF) 500 7 4 120 7 8 80 7 10 70 7 12 60 7 16 50 7 18 40 7 Use a crystal resonator with a frequency equal to the system clock frequency (). Notes on Board Design When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 16.4. When the board is designed, the crystal resonator and its load capacitors should be placed as close as possible to the XTAL and EXTAL pins. Avoid C L2 XTAL Signal A Signal B LSI EXTAL C L1 Figure 16.4 Example of Incorrect Board Design Rev.3.00 Mar. 26, 2007 Page 500 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator 16.2.2 External Clock Input Circuit Configuration An external clock signal can be input as shown in the examples in figure 16.5. In example b, the clock should be held high in standby mode. If the XTAL pin is left open, the stray capacitance should not exceed 10 pF. EXTAL External clock input XTAL Open a. XTAL pin left open EXTAL External clock input XTAL 74HC04 b. Complementary clock input at XTAL pin Figure 16.5 External Clock Input (Examples) Rev.3.00 Mar. 26, 2007 Page 501 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator External Clock The external clock frequency should be equal to the system clock frequency (). Table 16.3 and figure 16.6 indicate the clock timing. Table 16.3 Clock Timing VCC = 2.7 V to 5.5 V Item External clock rise time External clock fall time External clock input duty (a/tcyc) clock width duty (b/tcyc) -- Symbol tEXr tEXf -- Min -- -- 30 40 40 Max 10 10 70 60 60 VCC = 5.0 V 10% Min -- -- 30 40 40 Max 5 5 70 60 60 Unit ns ns % % % 5 MHz < 5 MHz Figure 16.6 Test Conditions Figure 16.6 tcyc a EXTAL VCC x 0.5 tEXr tEXf tcyc b VCC x 0.5 Figure 16.6 External Clock Input Timing Rev.3.00 Mar. 26, 2007 Page 502 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator Table 16.4 and figure 16.7 show the timing for the external clock output stabilization delay time. The oscillator and duty correction circuit have the function of regulating the waveform of the external clock input to the EXTAL pin. When the specified clock signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the external clock output stabilization delay time (tDEXT). As clock signal output is not confirmed during the tDEXT period, the reset signal should be driven low and the reset state maintained during this time. Table 16.4 External Clock Output Stabilization Delay Time Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V Item External clock output stabilization delay time Note: * Symbol tDEXT* Min 500 Max -- Unit s Notes Figure 16.7 tDEXT includes a 10 tcyc RES pulse width (tRESW). VCC 2.7 V STBY EXTAL VIH RES tDEXT* Note: * tDEXT includes a 10 tcyc RES pulse width (tRESW). Figure 16.7 External Clock Output Stabilization Delay Time Rev.3.00 Mar. 26, 2007 Page 503 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator 16.3 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (). 16.4 Prescalers The prescalers divide the system clock () to generate internal clocks (/2 to /4096). 16.5 Frequency Divider The frequency divider divides the duty-adjusted clock signal to generate the system clock (). The frequency division ratio can be changed dynamically by modifying the value in DIVCR, as described below. Power consumption in the chip is reduced in almost direct proportion to the frequency division ratio. The system clock generated by the frequency divider can be output at the pin. 16.5.1 Register Configuration Table 16.5 summarizes the frequency division register. Table 16.5 Frequency Division Register Address* H'FF5D Note: * Name Division control register Abbreviation DIVCR R/W R/W Initial Value H'FC The lower 16 bits of the address are shown. Rev.3.00 Mar. 26, 2007 Page 504 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator 16.5.2 Division Control Register (DIVCR) DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency divider. Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 DIV1 0 R/W 0 DIV0 0 R/W Reserved bits Divide bits 1 and 0 These bits select the frequency division ratio DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 2--Reserved: These bits cannot be modified and are always read as 1. Bits 1 and 0--Divide (DIV1 and DIV0): These bits select the frequency division ratio, as follows. Bit 1 DIV1 0 0 1 1 Bit 0 DIV0 0 1 0 1 Frequency Division Ratio 1/1 1/2 1/4 1/8 (Initial value) Rev.3.00 Mar. 26, 2007 Page 505 of 682 REJ09B0353-0300 Section 16 Clock Pulse Generator 16.5.3 Usage Notes The DIVCR setting changes the frequency, so note the following points. * Select a frequency division ratio that stays within the assured operation range specified for the clock cycle time tcyc in the AC electrical characteristics. Note that MIN = 1 MHz. Avoid settings that give system clock frequencies less than 1 MHz. All on-chip module operations are based on . Note that the timing of timer operations, serial communication, and other time-dependent processing differs before and after any change in the division ratio. The waiting time for exit from software standby mode also changes when the division ratio is changed. For details, see section 17.4.3, Selection of Oscillator Waiting Time after Exit from Software Standby Mode Rev.3.00 Mar. 26, 2007 Page 506 of 682 REJ09B0353-0300 Section 17 Power-Down State Section 17 Power-Down State 17.1 Overview This LSI has a power-down state that greatly reduces power consumption by halting CPU functions, and a module standby function that reduces power consumption by selectively halting on-chip modules. The power-down state includes the following three modes: * Sleep mode * Software standby mode * Hardware standby mode The module standby function can halt on-chip supporting modules independently of the powerdown state. The modules that can be halted are the ITU, SCI0, SCI1, and A/D converter. Table 17.1 indicates the methods of entering and exiting these power-down modes and the status of the CPU and on-chip supporting modules in each mode. Rev.3.00 Mar. 26, 2007 Page 507 of 682 REJ09B0353-0300 State CPU Registers ITU Active Active Active Active Active Held output Held * Interrupt * RES * STBY * * * * NMI IRQ0 to IRQ1 RES STBY * STBY * RES * STBY * RES * Clear MSTCR bit to 0*3 -- SCI0 SCI1 A/D Supporting Modules RAM Held I/O Ports Exiting Methods Mode Halted Entering Conditions CPU Clock clock output Sleep mode SLEEP instruc- Active tion executed while SSBY = 0 in SYSCR Halted Held Halted and reset Halted and reset Halted*1 Halted*1 and and reset reset Halted*1 Halted*1 and and reset reset Active -- High impedance*1 Halted and reset Halted and reset Halted and reset Halted and reset Held*2 High impedance High impedance Halted and reset Halted and reset Halted and reset Halted and reset Held High output Held Software standby mode Halted Undeter mined -- SLEEP instruc- Halted tion executed while SSBY = 1 in SYSCR Section 17 Power-Down State Hardware Low input at standby STBY pin mode Active Halted Rev.3.00 Mar. 26, 2007 Page 508 of 682 REJ09B0353-0300 Module standby function Corresponding bit set to 1 in MSTCR Active Legend: SYSCR: SSBY: MSTCR: System control register Software standby bit Module standby control register Notes: 1. State in which the corresponding MSTCR bit was set to 1. For details see section 17.2.2, Module Standby Control Register (MSTCR). 2. The RAME bit must be cleared to 0 in SYSCR before the transition from the program execution state to hardware standby mode. Table 17.1 Power-Down State and Module Standby Function 3. When a MSTCR bit is set to 1, the registers of the corresponding on-chip supporting module are initialized. To restart the module, first clear the MSTCR bit to 0, then set up the module registers again. Section 17 Power-Down State 17.2 Register Configuration This LSI has a system control register (SYSCR) that controls the power-down state, and a module standby control register (MSTCR) that controls the module standby function. Table 17.2 summarizes this register. Table 17.2 Register Configuration Address* H'FFF2 H'FF5E Note: * Name System control register Module standby control register Lower 16 bits of the address. Abbreviation SYSCR MSTCR R/W R/W R/W Initial Value H'0B H'40 17.2.1 Bit System Control Register (SYSCR) 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 UE 1 R/W 2 NMIEG 0 R/W 1 -- 1 -- 0 RAME 1 R/W RAM enable Initial value Read/Write Reserved bit NMI edge select User bit enable Standby timer select 2 to 0 These bits select the waiting time at exit from software standby mode Software standby Enables transition to software standby mode SYSCR is an 8-bit readable/writable register. Bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0) control the power-down state. For information on the other SYSCR bits, see section 3.3, System Control Register (SYSCR). Rev.3.00 Mar. 26, 2007 Page 509 of 682 REJ09B0353-0300 Section 17 Power-Down State Bit 7--Software Standby (SSBY): Enables transition to software standby mode. When software standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal operation. To clear this bit, write 0. Bit 7 SSBY 0 1 Description SLEEP instruction causes transition to sleep mode SLEEP instruction causes transition to software standby mode (Initial value) Bits 6 to 4--Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the clock to settle when software standby mode is exited by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to the clock frequency so that the waiting time (for the clock to stabilize) will be at least 7 ms. See table 17.3. If an external clock is used, any setting is permitted. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 0 1 -- Description Waiting time = 8192 states Waiting time = 16384 states Waiting time = 32768 states Waiting time = 65536 states Waiting time = 131072 states Waiting time = 1024 states Illegal setting (Initial value) Rev.3.00 Mar. 26, 2007 Page 510 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.2.2 Module Standby Control Register (MSTCR) MSTCR is an 8-bit readable/writable register that controls output of the system clock (). It also controls the module standby function, which places individual on-chip supporting modules in the standby state. Module standby can be designated for the ITU, SCI0, SCI1, and A/D converter modules. Bit Initial value Read/Write 7 PSTOP 0 R/W 6 -- 1 -- Reserved bit clock stop Enables or disables output of the system clock Module standby 5 to 3, and 0 These bits select modules to be placed in standby 5 0 R/W 4 0 R/W 3 0 R/W 2 -- 0 -- 1 -- 0 -- 0 MSTOP0 0 R/W MSTOP5 MSTOP4 MSTOP3 Reserved bit MSTCR is initialized to H'40 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7-- Clock Stop (PSTOP): Enables or disables output of the system clock (). Bit 7 PSTOP 0 1 Description System clock output is enabled System clock output is disabled (Initial value) Bit 6--Reserved: This bit cannot be modified and is always read as 1. Bit 5--Module Standby 5 (MSTOP5): Selects whether to place the ITU in standby. Bit 5 MSTOP5 0 1 Description ITU operates normally ITU is in standby state (Initial value) Rev.3.00 Mar. 26, 2007 Page 511 of 682 REJ09B0353-0300 Section 17 Power-Down State Bit 4--Module Standby 4 (MSTOP4): Selects whether to place SCI0 in standby. Bit 4 MSTOP4 0 1 Description SCI0 operates normally SCI0 is in standby state (Initial value) Bit 3--Module Standby 3 (MSTOP3): Selects whether to place SCI1 in standby. Bit 3 MSTOP3 0 1 Description SCI1 operates normally SCI1 is in standby state (Initial value) Bits 2 to 1--Reserved: Bits 2 to 1 are reserved. Bit 0--Module Standby 0 (MSTOP0): Selects whether to place the A/D converter in standby. Bit 0 MSTOP0 0 1 Description A/D converter operates normally A/D converter is in standby state (Initial value) Rev.3.00 Mar. 26, 2007 Page 512 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.3 17.3.1 Sleep Mode Transition to Sleep Mode When the SSBY bit is cleared to 0 in the system control register (SYSCR), execution of the SLEEP instruction causes a transition from the program execution state to sleep mode. Immediately after executing the SLEEP instruction the CPU halts, but the contents of its internal registers are retained. The on-chip supporting modules do not halt in sleep mode. On-chip supporting modules which have been placed in standby by the module standby function, however, remain halted. 17.3.2 Exit from Sleep Mode Sleep mode is exited by an interrupt, or by input at the RES or STBY pin. Exit by Interrupt: An interrupt terminates sleep mode and causes a transition to the interrupt exception handling state. Sleep mode is not exited by an interrupt source in an on-chip supporting module if the interrupt is disabled in the on-chip supporting module. Sleep mode is not exited by an interrupt other then NMI if the interrupt is masked by interrupt priority settings (IPR) and the settings of the I and UI bits in CCR. Exit by RES Input: Low input at the RES pin exits from sleep mode to the reset state. Exit by STBY Input: Low input at the STBY pin exits from sleep mode to hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 513 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.4 17.4.1 Software Standby Mode Transition to Software Standby Mode To enter software standby mode, execute the SLEEP instruction while the SSBY bit is set to 1 in SYSCR. In software standby mode, current dissipation is reduced to an extremely low level because the CPU, clock, and on-chip supporting modules all halt. The on-chip supporting modules are reset and halted. As long as the specified voltage is supplied, however, CPU register contents and onchip RAM data are retained. The settings of the I/O ports are also held. 17.4.2 Exit from Software Standby Mode Software standby mode can be exited by input of an external interrupt at the NMI, IRQ0, IRQ1, or by input at the RES or STBY pin. Exit by Interrupt: When an NMI, IRQ0, or IRQ1 interrupt request signal is received, the clock oscillator begins operating. After the oscillator settling time selected by bits STS2 to STS0 in SYSCR, stable clock signals are supplied to the entire chip, software standby mode ends, and interrupt exception handling begins. Software standby mode is not exited if the interrupt enable bits of interrupts IRQ0, and IRQ1 are cleared to 0, or if these interrupts are masked in the CPU. Exit by RES Input: When the RES input goes low, the clock oscillator starts and clock pulses are supplied immediately to the entire chip. The RES signal must be held low long enough for the clock oscillator to stabilize. When RES goes high, the CPU starts reset exception handling. Exit by STBY Input: Low input at the STBY pin causes a transition to hardware standby mode. Rev.3.00 Mar. 26, 2007 Page 514 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.4.3 Selection of Oscillator Waiting Time after Exit from Software Standby Mode Bits STS2 to STS0 in SYSCR, and its DIV1 and DIV0 in DIVCR should be set as follows. Crystal Resonator Set STS2 to STS0, and DIV1 and DIV0 so that the waiting time (for the clock to stabilize) is at least 7 ms. Table 17.3 indicates the waiting times that are selected by STS2 to STS0, and DIV1 and DIV0 settings at various system clock frequencies. External Clock Any value may be set. Table 17.3 Clock Frequency and Waiting Time for Clock to Settle DIV1 0 DIV0 0 STS2 0 0 0 0 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 STS1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 1 0 0 1 STS0 0 1 0 1 0 1 -- 0 1 0 1 0 1 -- 0 1 0 1 0 1 -- 0 1 0 1 0 1 -- Waiting Time 8192 states 16384 states 32768 states 65536 states 131072 states 1024 states Illegal setting 8192 states 16384 states 32768 states 65536 states 131072 states 1024 states Illegal setting 8192 states 16384 states 32768 states 65536 states 131072 states 1024 states Illegal setting 8192 states 16384 states 32768 states 65536 states 131072 states 1024 states Illegal setting 18 MHz 0.46 0.91 1.8 3.6 7.3 0.057 0.91 1.8 3.6 7.3 14.6 0.11 1.8 3.6 7.3 14.6 29.1 0.23 3.6 7.3 14.6 29.1 58.3 0.46 16 MHz 0.51 1.0 2.0 4.1 8.2 0.064 1.02 2.0 4.1 8.2 16.4 0.13 2.0 4.1 8.2 16.4 32.8 0.26 4.1 8.2 16.4 32.8 65.5 0.51 12 MHz 0.65 1.3 2.7 5.5 10.9 0.085 1.4 2.7 5.5 10.9 21.8 0.17 2.7 5.5 10.9 21.8 43.7 0.34 5.5 10.9 21.8 43.7 87.4 0.68 10 MHz 0.8 1.6 3.3 6.6 13.1 0.10 1.6 3.3 6.6 13.1 26.2 0.20 3.3 6.6 13.1 26.2 52.4 0.41 6.6 13.1 26.2 52.4 104.9 0.82 8 MHz 1.0 2.0 4.1 8.2 16.4 0.13 2.0 4.1 8.2 16.4 32.8 0.26 4.1 8.2 16.4 32.8 65.5 0.51 8.2 16.4 32.8 65.5 131.1 1.0 6 MHz 1.3 2.7 5.5 10.9 21.8 0.17 2.7 5.5 10.9 21.8 43.7 0.34 5.5 10.9 21.8 43.7 87.4 0.68 10.9 21.8 43.7 87.4 174.8 1.4 4 MHz 2.0 4.1 8.2 16.4 32.8 0.26 4.1 8.2 16.4 32.8 65.5 0.51 8.2 16.4 32.8 65.5 131.1 1.02 16.4 32.8 65.5 131.1 262.1 2.0 2 MHz 4.1 8.2 16.4 32.8 65.5 0.51 8.2 16.4 32.8 65.5 131.1 1.0 16.4 32.8 65.5 131.1 262.1 2.0 32.8 65.5 131.1 262.1 524.3 4.1 1 MHz 8.2 16.4 32.8 65.5 131.1 1.0 16.4 32.8 65.5 131.1 262.1 2.0 32.8 65.5 131.1 262.1 524.3 4.1 65.5 131.1 262.1 524.3 1048.6 8.2 ms ms ms Unit ms : Recommended setting Rev.3.00 Mar. 26, 2007 Page 515 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.4.4 Sample Application of Software Standby Mode Figure 17.1 shows an example in which software standby mode is entered at the fall of NMI and exited at the rise of NMI. With the NMI edge select bit (NMIEG) cleared to 0 in SYSCR (selecting the falling edge), an NMI interrupt occurs. Next the NMIEG bit is set to 1 (selecting the rising edge) and the SSBY bit is set to 1; then the SLEEP instruction is executed to enter software standby mode. Software standby mode is exited at the next rising edge of the NMI signal. Clock oscillator NMI NMIEG SSBY NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (powerdown state) Oscillator settling time (t osc2 ) NMI exception handling SLEEP instruction Figure 17.1 NMI Timing for Software Standby Mode (Example) 17.4.5 Usage Note The I/O ports retain their existing states in software standby mode. If a port is in the high output state, its output current is not reduced. Rev.3.00 Mar. 26, 2007 Page 516 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.5 17.5.1 Hardware Standby Mode Transition to Hardware Standby Mode Regardless of its current state, the chip enters hardware standby mode whenever the STBY pin goes low. Hardware standby mode reduces power consumption drastically by halting all functions of the CPU and on-chip supporting modules. All modules are reset except the on-chip RAM. As long as the specified voltage is supplied, on-chip RAM data is retained. I/O ports are placed in the high-impedance state. Clear the RAME bit to 0 in SYSCR before STBY goes low to retain on-chip RAM data. The inputs at the mode pins (MD2 to MD0) should not be changed during hardware standby mode. 17.5.2 Exit from Hardware Standby Mode Hardware standby mode is exited by inputs at the STBY and RES pins. While RES is low, when STBY goes high, the clock oscillator starts running. RES should be held low long enough for the clock oscillator to settle. When RES goes high, reset exception handling begins, followed by a transition to the program execution state. Rev.3.00 Mar. 26, 2007 Page 517 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.5.3 Timing for Hardware Standby Mode Figure 17.2 shows the timing relationships for hardware standby mode. To enter hardware standby mode, first drive RES low, then drive STBY low. To exit hardware standby mode, first drive STBY high, wait for the clock to settle, then bring RES from low to high. Clock oscillator RES STBY Oscillator settling time Reset exception handling Figure 17.2 Hardware Standby Mode Timing Rev.3.00 Mar. 26, 2007 Page 518 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.6 17.6.1 Module Standby Function Module Standby Timing The module standby function can halt several of the on-chip supporting modules (the ITU, SCI0, SCI1, and A/D converter) independently of the power-down state. This standby function is controlled by bits MSTOP5 to MSTOP3 and MSTOP0 in MSTCR. When one of these bits is set to 1, the corresponding on-chip supporting module is placed in standby and halts at the beginning of the next bus cycle after the MSTCR write cycle. 17.6.2 Read/Write in Module Standby When an on-chip supporting module is in module standby, read/write access to its registers is disabled. Read access always results in H'FF data. Write access is ignored. 17.6.3 Usage Notes When using the module standby function, note the following points. Cancellation of Interrupt Handling: When an on-chip supporting module is placed in standby by the module standby function, its registers are initialized, including registers with interrupt request flags. Consequently, if an interrupt occurs just before the MSTOP bit is set to 1, the interrupt will not be recognized. The interrupt source will not be held pending. Pin States: Pins used by an on-chip supporting module lose their module functions when the module is placed in module standby. What happens after that depends on the particular pin. For details, see section 7, I/O Ports. Pins that change from the input to the output state require special care. For example, if SCI1 is placed in module standby, the receive data pin loses its receive data function and becomes a generic I/O pin. If its data direction bit is set to 1, the pin becomes a data output pin, and its output may collide with external serial data. Data collisions should be prevented by clearing the data direction bit to 0 or taking other appropriate action. Register Resetting: When an on-chip supporting module is halted by the module standby function, all its registers are initialized. To restart the module, after its MSTOP bit is cleared to 0, its registers must be set up again. It is not possible to write to the registers while the MSTOP bit is set to 1. Rev.3.00 Mar. 26, 2007 Page 519 of 682 REJ09B0353-0300 Section 17 Power-Down State 17.7 System Clock Output Disabling Function Output of the system clock () can be controlled by the PSTOP bit in MSTCR. When the PSTOP bit is set to 1, output of the system clock halts and the pin is placed in the high-impedance state. Figure 17.3 shows the timing of the stopping and starting of system clock output. When the PSTOP bit is cleared to 0, output of the system clock is enabled. Table 17.4 indicates the state of the pin in various operating states. MSTCR write cycle (PSTOP = 1) T1 pin High impedance T2 T3 MSTCR write cycle (PSTOP = 0) T1 T2 T3 Figure 17.3 Starting and Stopping of System Clock Output Table 17.4 Pin State in Various Operating States Operating State Hardware standby Software standby Sleep mode Normal operation PSTOP = 0 High impedance Always high System clock output System clock output PSTOP = 1 High impedance High impedance High impedance High impedance Rev.3.00 Mar. 26, 2007 Page 520 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Section 18 Electrical Characteristics 18.1 18.1.1 Electrical Characteristics of Mask ROM Version Absolute Maximum Ratings Table 18.1 lists the absolute maximum ratings. Table 18.1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 7)* Input voltage (port 7) Analog power supply voltage Analog input voltage Operating temperature Symbol VCC Vin Vin AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature Caution: Note: * -55 to +125 Unit V V V V V C C C Permanent damage to the chip may result if absolute maximum ratings are exceeded. 12 V must not be applied to any pin, as this will cause permanent damage to the chip. Rev.3.00 Mar. 26, 2007 Page 521 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.1.2 DC Characteristics Table 18.2 lists the DC characteristics. Table 18.3 lists the permissible output currents. Table 18.2 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Port A, Schmitt trigger input P80 to P81, voltages PB0 to PB3 Input high voltage RES, STBY, NMI, MD2, MD1, MD0 EXTAL Port 7 Ports 1, 2, 3, 5, 6, 9, PB4, PB5, PB7 Input low voltage RES, STBY, MD2, MD1, MD0 NMI, EXTAL, ports 1, 2, 3, 5, 6, 7, 9, PB4, PB5, PB7 Output high All output pins voltage (except RESO) Output low voltage All output pins (except RESO) Ports 1, 2, 5, B RESO VOH VOL VIL Symbol VT VT - + + - 1 Min 1.0 -- 0.4 VCC -0.7 Typ -- -- -- -- Max -- VCC x 0.7 -- VCC +0.3 Unit Test Conditions V V V V VT - VT VIH VCC x 0.7 2.0 2.0 -- -- -- VCC +0.3 VCC +0.3 V AVCC +0.3 V V -0.3 -0.3 -- -- 0.5 0.8 V V VCC -0.5 3.5 -- -- -- -- -- -- -- -- -- -- 0.4 1.0 0.4 V V V V V IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 10 mA IOL = 2.6 mA Rev.3.00 Mar. 26, 2007 Page 522 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Item Input leakage current Symbol STBY, NMI, |Iin| RES, MD2, MD1, MD0 Port 7 Three-state Ports 1, 2, 3, 5, |ITSI| leakage 6, 8 to B current RESO (off state) Input Ports 2, 5 pull-up MOS current -Ip Min -- Typ -- Max 1.0 Unit Test Conditions A Vin = 0.5 to VCC -0.5 V Vin = 0.5 to AVCC -0.5 V Vin = 0.5 to VCC -0.5 V -- -- -- 50 -- -- -- -- 1.0 1.0 10.0 300 A A A A Vin = 0 V Input NMI, RES Cin capacitance All input pins except NMI and RES Current Normal 2 dissipation* operation Sleep mode Standby mode* 3 -- -- -- -- 50 20 pF Vin = 0 V, f = 1 MHz, Ta = 25C f = 18 MHz f = 18 MHz ICC -- -- -- -- 50 35 0.01 -- 1.7 0.02 -- 70 50 5.0 20.0 2.8 10.0 -- mA A Ta 50C 50C < Ta Analog power supply current During A/D conversion Idle AICC -- -- mA A V RAM standby voltage VRAM 2.0 Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Connect AVCC to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 4.5 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. Rev.3.00 Mar. 26, 2007 Page 523 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.2 DC Characteristics (2) Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Schmitt Port A, trigger input P80 to P81, voltages PB0 to PB3 Input high voltage Symbol VT VT - + + - 1 Min VCC x 0.2 -- VCC x 0.9 Typ -- -- Max -- VCC x 0.7 -- VCC +0.3 Unit Test Conditions V V V V VT - VT VCC x 0.04 -- -- RES, STBY, VIH NMI, MD2, MD1, MD0 EXTAL Port 7 Ports 1, 2, 3, 5, 6, 9, PB4, PB5, PB7 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- VCC +0.3 VCC +0.3 V AVCC +0.3 V V Input low voltage RES, STBY, MD2, MD1, MD0 NMI, EXTAL, ports 1, 2, 3, 5, 6, 7, 9, PB4, PB5, PB7 VIL -0.3 -0.3 -- -- VCC x 0.1 VCC x 0.2 0.8 V V V VCC < 4.0 V VCC = 4.0 V to 5.5 V IOH = -200 A IOH = -1 mA IOL = 1.0 mA VCC 4 V, IOL = 5 mA, 4 V < VCC 5.5 V, IOL = 10 mA IOL = 1.6 mA Vin = 0.5 V to VCC -0.5 V Vin = 0.5 V to AVCC -0.5 V Output high All output pins voltage (except RESO) Output low voltage All output pins (except RESO) Ports 1, 2, 5, B VOH VOL VCC -0.5 VCC -1.0 -- -- -- -- -- -- -- -- 0.4 1.0 V V V V RESO Input leakage current |Iin| STBY, NMI, RES, MD2, MD1, MD0 Port 7 -- -- -- -- 0.4 1.0 V A -- -- 1.0 A Rev.3.00 Mar. 26, 2007 Page 524 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Item Symbol Min -- -- 10 Typ -- -- -- Max 1.0 10.0 300 Unit Test Conditions A A A VCC = 2.7 V to 5.5 V, Vin = 0 V Vin = 0 V, f = 1 MHz , Ta = 25C Vin = 0.5 V to VCC -0.5 V Three-state Ports 1, 2, 3, 5, |ITSI| 6, 8, 9, A, B leakage current RESO (off state) Input Ports 2, 5 pull-up MOS current Input NMI, RES capacitance All input pins except NMI and RES Current Normal 2 dissipation* operation Sleep mode Standby mode* 3 -Ip Cin -- -- -- -- 50 20 pF ICC* 4 -- -- -- -- 12 33.8 (3.0 V) (5.5 V) 8 25.0 (3.0 V) (5.5 V) 0.01 -- 1.3 1.7 0.02 -- 5.0 20.0 2.5 2.8 10.0 -- mA mA A A mA mA A V f = 8 MHz f = 8 MHz Ta 50C 50C < Ta AVCC = 3.0 V AVCC = 5.0 V Analog power supply current During A/D conversion Idle AICC -- -- -- RAM standby voltage VRAM 2.0 Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Connect AVCC to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up MOS transistors in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 3.0 (mA) + 0.7 (mA/MHz * V) x VCC x f [normal mode] ICC max = 3.0 (mA) + 0.5 (mA/MHz * V) x VCC x f [sleep mode] Rev.3.00 Mar. 26, 2007 Page 525 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.2 DC Characteristics (3) Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Schmitt Port A, trigger input P80 to P81, voltages PB0 to PB3 Input high voltage Symbol VT VT - + + - 1 Min VCC x 0.2 -- VCC x 0.9 Typ -- -- Max -- VCC x 0.7 -- VCC +0.3 Unit Test Conditions V V V V VT - VT VCC x 0.04 -- -- RES, STBY, VIH NMI, MD2, MD1, MD0 EXTAL Port 7 Ports 1, 2, 3, 5, 6, 9, PB4, PB5, PB7 VCC x 0.7 VCC x 0.7 VCC x 0.7 -- -- -- VCC +0.3 VCC +0.3 V AVCC +0.3 V V Input low voltage RES, STBY, MD2, MD1, MD0 NMI, EXTAL, ports 1, 2, 3, 5, 6, 7, 9, PB4, PB5, PB7 VIL -0.3 -0.3 -- -- VCC x 0.1 VCC x 0.2 0.8 V V V VCC < 4.0 V VCC = 4.0 V to 5.5 V IOH = -200 A IOH = -1 mA IOL = 1.0 mA VCC 4 V, IOL = 5 mA, 4 V < VCC 5.5 V, IOL = 10 mA IOL = 1.6 mA Vin = 0.5 V to VCC -0.5 V Vin = 0.5 V to AVCC -0.5 V Output high All output pins voltage (except RESO) Output low voltage All output pins (except RESO) Ports 1, 2, 5, B VOH VOL VCC -0.5 VCC -1.0 -- -- -- -- -- -- -- -- 0.4 1.0 V V V V RESO Input leakage current |Iin| STBY, NMI, RES, MD2, MD1, MD0 Port 7 -- -- -- -- 0.4 1.0 V A -- -- 1.0 A Rev.3.00 Mar. 26, 2007 Page 526 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Item Symbol Min -- -- 10 Typ -- -- -- Max 1.0 10.0 300 Unit Test Conditions A A A VCC = 3.0 V to 5.5 V, Vin = 0 V Vin = 0 V, f = 1 MHz, Ta = 25C f = 10 MHz f = 10 MHz Ta 50C 50C < Ta AVCC = 3.0 V AVCC = 5.0 V Vin = 0.5 V to VCC -0.5 V Three-state Ports 1, 2, 3, 5, |ITSI| 6, 8 to B leakage current RESO (off state) Input Ports 2, 5 pull-up MOS current Input NMI, RES capacitance All input pins except NMI and RES Current Normal 2 dissipation* operation Sleep mode Standby mode* 3 -Ip Cin -- -- -- -- 50 20 pF ICC* 4 -- -- -- -- 15 41.5 (3.0 V) (5.5 V) 10 30.5 (3.0 V) (5.5 V) 0.01 -- 1.3 1.7 0.02 -- 5.0 20.0 2.5 -- 10.0 -- mA mA A A mA mA A V Analog power supply current During A/D conversion Idle AICC -- -- -- RAM standby voltage VRAM 2.0 Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Connect AVCC to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 3.0 (mA) + 0.7 (mA/MHz * V) x VCC x f [normal mode] ICC max = 3.0 (mA) + 0.5 (mA/MHz * V) x VCC x f [sleep mode] Rev.3.00 Mar. 26, 2007 Page 527 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.3 Permissible Output Currents Conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Ports 1, 2, 5 and B Other output pins Total of 27 pins including ports 1, 2, 5 and B Total of 23 pins, including ports 8, 9, A and B Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins IOH IOH IOL Symbol IOL Min -- -- -- -- -- -- -- Typ -- -- -- -- -- -- -- Max 10 2.0 80 75* /65* 120 2.0 40 2 1 Unit mA mA mA mA mA mA mA Notes: To protect chip reliability, do not exceed the output current values in table 18.3. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 18.1 and 18.2. 1. The value is for conditions: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V 2. The value is for conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V Rev.3.00 Mar. 26, 2007 Page 528 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics LSI 2 k Port Darlington pair Figure 18.1 Darlington Pair Drive Circuit (Example) LSI Ports 600 LED Figure 18.2 LED Drive Circuit (Example) Rev.3.00 Mar. 26, 2007 Page 529 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.1.3 AC Characteristics Bus timing parameters are listed in table 18.4. Control signal timing parameters are listed in table 18.5. Timing parameters of the on-chip supporting modules are listed in table 18.6. Table 18.4 Bus Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 8 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 8 MHz Item Clock cycle time Clock low pulse width Clock high pulse width Clock rise time Clock fall time Address delay time Address hold time Address strobe delay time Write strobe delay time Strobe delay time Write data strobe pulse width 1 Write data strobe pulse width 2 Address setup time 1 Address setup time 2 Read data setup time Read data hold time Symbol tcyc tCL tCH tCr tCf tAD tAH tASD tWSD tSD tWSW1* tWSW2* tAS1 tAS2 tRDS tRDH Min 125 40 40 -- -- -- 25 -- -- -- 85 150 20 80 50 0 Max 500 -- -- 20 20 60 -- 60 60 60 -- -- -- -- -- -- Condition B 10 MHz Min 100 30 30 -- -- -- 20 -- -- -- 60 110 15 65 35 0 Max 500 -- -- 15 15 50 -- 40 50 50 -- -- -- -- -- -- Condition C 18 MHz Min 55.5 17 17 -- -- -- 10 -- -- -- 32 62 10 38 15 0 Max 500 -- -- 10 10 25 -- 25 25 25 -- -- -- -- -- -- Unit ns Test Conditions Figure 18.7, Figure 18.8 Rev.3.00 Mar. 26, 2007 Page 530 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Condition A 8 MHz Item Write data delay time Write data setup time 1 Write data setup time 2 Write data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Precharge time Wait setup time Wait hold time Symbol tWDD tWDS1 tWDS2 tWDH tACC1* tACC2* tACC3* tACC4* tPCH* tWTS tWTH Min -- 60 5 25 -- -- -- -- 85 40 10 Max 75 -- -- -- 120 240 70 180 -- -- -- -- 40 -10 20 -- -- -- -- 60 40 10 Condition B 10 MHz Min Max 75 -- -- -- 100 200 50 150 -- -- -- -- 10 -10 20 -- -- -- -- 40 25 5 Condition C 18 MHz Min Max 55 -- -- -- 50 105 20 80 -- -- -- Figure 18.9 Unit ns Test Conditions Figure 18.7, Figure 18.8 Note: * For Condition A, the following times depend on the clock cycle time as shown below. tACC1 = 1.5 x tcyc -68 (ns) tWSW1 = 1.0 x tcyc -40 (ns) tACC2 = 2.5 x tcyc -73 (ns) tWSW2 = 1.5 x tcyc -38 (ns) tACC3 = 1.0 x tcyc -55 (ns) tPCH = 1.0 x tcyc -40 (ns) tACC4 = 2.0 x tcyc -70 (ns) For Condition B, the following times depend on the clock cycle time as shown below. tACC1 = 1.5 x tcyc -50 (ns) tWSW1 = 1.0 x tcyc -40 (ns) tACC2 = 2.5 x tcyc -50 (ns) tWSW2 = 1.5 x tcyc -40 (ns) tACC3 = 1.0 x tcyc -50 (ns) tPCH = 1.0 x tcyc -40 (ns) tACC4 = 2.0 x tcyc -50 (ns) For Condition C, the following times depend on the clock cycle time as shown below. tACC1 = 1.5 x tcyc -34 (ns) tWSW1 = 1.0 x tcyc -24 (ns) tACC2 = 2.5 x tcyc -34 (ns) tWSW2 = 1.5 x tcyc -22 (ns) tACC3 = 1.0 x tcyc -36 (ns) tPCH = 1.0 x tcyc -21 (ns) tACC4 = 2.0 x tcyc -31 (ns) Rev.3.00 Mar. 26, 2007 Page 531 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.5 Control Signal Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 8 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 8 MHz Item RES setup time RES pulse width Symbol tRESS tRESW Min 200 10 200 Max -- -- -- Condition B 10 MHz Min 200 10 200 Max -- -- -- Condition C 18 MHz Min 200 10 200 Max -- -- -- Unit ns tcyc ns Test Conditions Figure 18.10 Mode programming tMDS setup time (MD0, MD1, MD2) RESO output delay time RESO output pulse width NMI setup time (NMI, IRQ0, IRQ1, IRQ4, IRQ5) NMI hold time (NMI, IRQ0, IRQ1, IRQ4, IRQ5) tRESD tRESOW tNMIS -- 132 200 100 -- -- -- 132 200 100 -- -- -- 132 150 100 -- -- ns tcyc ns Figure 18.11 Figure 18.12 tNMIH 10 -- 10 -- 10 -- Interrupt pulse width tNMIW (NMI, IRQ1, IRQ0 when exiting software standby mode) Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) tOSC1 200 -- 200 -- 200 -- 20 -- 20 -- 20 -- ms Figure 18.13 tOSC2 8 -- 8 -- 7 -- ms Figure 17.1 Rev.3.00 Mar. 26, 2007 Page 532 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.6 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 8 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 8 MHz Item ITU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width SCI Input clock cycle Single edge Both edges Asynchronous Synchronous tSCKf tSCKW Symbol tTOCD tTICS tTCKS tTCKWH tTCKWL tScyc Min -- 50 50 1.5 2.5 4 6 -- -- 0.4 Max 100 -- -- -- -- -- -- 1.5 1.5 0.6 Condition B 10 MHz Min -- 50 50 1.5 2.5 4 6 -- -- 0.4 Max 100 -- -- -- -- -- -- 1.5 1.5 0.6 Condition C 18 MHz Min -- 50 50 1.5 2.5 4 6 -- -- 0.4 Max 100 -- -- -- -- -- -- 1.5 1.5 0.6 tScyc Figure 18.17 tcyc Figure 18.16 Unit ns Test Conditions Figure 18.15 Input clock rise time tSCKr Input clock fall time Input clock pulse width Rev.3.00 Mar. 26, 2007 Page 533 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Condition A 8 MHz Item SCI Symbol Transmit data delay tTXD time Receive data setup time (synchronous) Receive data hold time (synchronous clock input) Receive data hold time (synchronous clock output) Ports and TPC Output data delay time tPWD tRXS tRXH Min -- 100 100 Max 100 -- -- Condition B 10 MHz Min -- 100 100 Max 100 -- -- Condition C 18 MHz Min -- 100 100 Max 100 -- -- Unit ns Test Conditions Figure 18.18 0 -- 0 -- 0 -- -- 50 50 100 -- -- -- 50 50 100 -- -- -- 50 50 100 -- -- ns Figure 18.14 Input data setup time tPRS Input data hold time tPRH 5V C = 90 pF: ports 1, 2, 3, 5, 6, 8, RL This LSI output pin C = 30 pF: ports 9, A, B R L = 2.4 k R H = 12 k C RH Input/output timing measurement levels * Low: 0.8 V * High: 2.0 V Figure 18.3 Output Load Circuit Rev.3.00 Mar. 26, 2007 Page 534 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.1.4 A/D Conversion Characteristics Table 18.7 lists the A/D conversion characteristics. Table 18.7 A/D Converter Characteristics Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 8 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition B: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition C: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 8 MHz Item Resolution Conversion time Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 16.8 20 10*1 5* 2 Condition B 10 MHz Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 13.4 20 10*1 5* 3 Condition C 18 MHz Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 7.5 20 10*4 5* 5 Unit bits s pF k LSB LSB LSB LSB LSB 7.5 7.5 7.5 0.5 8.0 7.5 7.5 7.5 0.5 8.0 3.5 3.5 3.5 0.5 4.0 Notes: 1. 2. 3. 4. 5. The value is for 4.0 V AVCC 5.5 V. The value is for 2.7 V AVCC < 4.0 V. The value is for 3.0 V AVCC < 4.0 V. The value is for 12 MHz. The value is for > 12 MHz. Rev.3.00 Mar. 26, 2007 Page 535 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.2 18.2.1 Electrical Characteristics of Flash Memory Version Absolute Maximum Ratings Table 18.8 lists the absolute maximum ratings. Table 18.8 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 7)* Input voltage (port 7) Analog power supply voltage Analog input voltage Operating temperature 1 Symbol VCC Vin Vin AVCC VAN Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* 2 Unit V V V V V C 2 Wide-range specifications: -40 to +85* Storage temperature -55 to +125 C C Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded. Notes: 1. 12 V must not be applied to any pin, as this will cause permanent damage to the chip. 2. The operating temperature range when programming/erasing flash memory is Ta = 0 to +75C (regular specifications) or Ta = 0 to +85C (wide-range specifications). Rev.3.00 Mar. 26, 2007 Page 536 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.2.2 DC Characteristics Table 18.9 lists the DC characteristics. Table 18.10 lists the permissible output currents. Table 18.9 DC Characteristics (1) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) (Programming/Erasing Conditions: Ta = 0C to +75C (regular specifications), Ta = 0C to +85C (wide-range specifications)) Item Schmitt Port A, trigger input P80 to P81, PB0 to PB3 voltages Input high voltage Symbol VT VT - + + - 1 Min 1.0 -- 0.4 VCC -0.7 Typ -- -- -- -- Max -- VCC x 0.7 -- VCC +0.3 Unit Test Conditions V V V V VT - VT RES, STBY, VIH NMI, MD2, MD1, MD0, FWE EXTAL Port 7 Ports 1, 2, 3, 5, 6, 9, PB4, PB5, PB7 VCC x 0.7 2.0 2.0 -- -- -- VCC +0.3 VCC +0.3 V AVCC +0.3 V V Input low voltage RES, STBY, VIL MD2, MD1, MD0, FWE NMI, EXTAL, ports 1, 2, 3, 5, 6, 7, 9, PB4, PB5, PB7 -0.3 -- 0.5 V -0.3 -- 0.8 V Output high All output pins voltage Output low voltage All output pins Ports 1, 2, 5, B VOH VOL VCC -0.5 3.5 -- -- -- -- -- -- -- -- 0.4 1.0 V V V V IOH = -200 A IOH = -1 mA IOL = 1.6 mA IOL = 10 mA Rev.3.00 Mar. 26, 2007 Page 537 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Item Input leakage current Symbol STBY, NMI, |Iin| RES, MD2, MD1, MD0 Port 7 FWE Three-state Ports 1, 2, 3, leakage 5, 6, 8, 9, A, B current (off state) Input pull-up current Ports 2, 5 |ITSI| Min -- Typ -- Max 1.0 Unit Test Conditions A Vin = 0.5 V to VCC -0.5 V Vin = 0.5 V to AVCC -0.5 V Vin = 0.5 V to VCC -0.5 V -- -- -- -- -- -- 1.0 10 1.0 A A -Ip 50 -- 300 A Vin = 0 V Input NMI, RES capacitance All input pins except NMI and RES Current dissipation 2 4 ** Normal operation Sleep mode Standby mode* 3 Cin -- -- -- -- 50 20 pF Vin = 0 V, f = 1 MHz, Ta = 25C f = 18 MHz f = 18 MHz ICC -- -- -- -- 50 35 0.01 -- 1.7 0.02 -- 70 50 5.0 20.0 2.8 10.0 -- mA A Ta 50C 50C < Ta Analog power supply current During A/D conversion Idle AICC -- -- mA A V RAM standby voltage VRAM 2.0 Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Connect AVCC to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 4.5 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. Power supply current value when programming/erasing in flash memory (Ta = 0C to +75C (regular specifications), Ta = 0C to +85C (wide-range specifications)) is 20 mA (max) higher than the power supply current value in normal operation. Rev.3.00 Mar. 26, 2007 Page 538 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.9 DC Characteristics (2) Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V* , Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) (Programming/Erasing Conditions: VCC = 3.0 V to 3.6 V, Ta = 0C to +75C (regular specifications), Ta = 0C to +85C (wide-range specifications)) Item Schmitt Port A, trigger input P80 to P81, PB0 to PB3 voltages Input high voltage RES, STBY, NMI, MD2 to MD0, FWE EXTAL Port 7 Ports 1 to 3, 5, 6, 9, PB4, PB5, PB7 Input low voltage RES, STBY, FWE, MD2 to MD0, FWE NMI, EXTAL, ports 1 to 3, 5 to 7, 9, PB4, PB5, PB7 Output high All output pins voltage Output low voltage All output pins Ports 1, 2, 5, B VOH VIL Symbol VT VT - + + - 1 Min VCC x 0.2 -- VCC x 0.9 Typ -- -- Max -- VCC x 0.7 -- VCC +0.3 Unit Test Conditions V V V V VT - VT VIH VCC x 0.04 -- -- VCC x 0.7 VCC x 0.7 VCC x 0.7 -0.3 -- -- -- -- VCC +0.3 VCC +0.3 VCC x 0.1 V AVCC +0.3 V V V -0.3 -- VCC x 0.2 0.8 V VCC < 4.0 V VCC = 4.0 V to 5.5V VCC -0.5 VCC -1.0 -- -- -- -- -- -- 0.4 1.0 V V V V IOH = -200 A IOH = -1 mA IOL = 1.0 mA VCC 4 V, IOL = 5 mA, 4V < VCC 5.5 V, IOL = 10 mA VOL -- -- Rev.3.00 Mar. 26, 2007 Page 539 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Item Input leakage current STBY, NMI, RES, MD2, MD1, MD0 Port 7 FWE Three-state Ports 1, 2, 3, 5, |ITSI| leakage 6, 8 to B current (off state) Input pull-up Ports 2 and 5 current Input NMI, RES capacitance All input pins except NMI and RES Current dissipation 25 ** Normal operation Sleep mode Standby mode* 3 Symbol |Iin| Min -- Typ -- Max 1.0 Unit Test Conditions A Vin = 0.5 V to VCC -0.5 V Vin = 0.5 V to AVCC -0.5 V Vin = 0.5 V to VCC -0.5 V Vin = 0.5 V to VCC -0.5 V -- -- -- -- -- -- 1.0 10 1.0 A A A -Ip 10 -- 300 A VCC = 3.0 V to 5.5 V, Vin = 0 V Vin = 0 V, f = 1 MHz, Ta = 25C f = 10 MHz f = 10 MHz Ta 50C 50C < Ta AVCC = 3.0 V AVCC = 5.0 V Cin -- -- -- -- 50 20 pF pF ICC * 4 -- -- -- -- 15 (3.0 V) 10 (3.0 V) 0.01 -- 1.3 1.7 0.02 -- 41.5 (5.5 V) 30.5 (5.5 V) 5.0 20.0 2.5 2.8 10.0 -- mA mA A Analog power supply current During A/D conversion Idel AICC -- -- -- mA A V RAM standby voltage VRAM 2.0 Notes: 1. If the A/D converter is not used, do not leave the AVCC and AVSS pins open. Connect AVCC to VCC, and connect AVSS to VSS. 2. Current dissipation values are for VIH min = VCC -0.5 V and VIL max = 0.5 V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 3.0 V, VIH min = VCC x 0.9, and VIL max = 0.3 V. 4. ICC depends on VCC and f as follows: ICC max = 3.0 (mA) + 0.7 (mA/MHz V) x VCC x f [normal mode] ICC max = 3.0 (mA) + 0.5 (mA/MHz V) x VCC x f [sleep mode] 5. The current dissipation value when programming/erasing flash memory (Ta = 0C to +75C (regular specifications), Ta = 0C to +85C (wide-range specifications)) is 20 mA (max) higher than the current dissipation value in normal operation. Rev.3.00 Mar. 26, 2007 Page 540 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.10 Permissible Output Currents Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Item Permissible output low current (per pin) Ports 1, 2, 5 and B Other output pins Permissible output low current (total) Total of 27 pins including ports 1, 2, 5 and B Total of 23 pins, including ports 8, 9, A and B Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins IOH IOH IOL Symbol IOL Min -- -- -- Typ -- -- -- Max 10 2.0 80 Unit mA mA mA -- -- 75* / 1 65* 120 2.0 40 2 mA -- -- -- -- -- -- mA mA mA Notes: To protect chip reliability, do not exceed the output current values in table 18.10. When driving a Darlington pair or LED, always insert a current-limiting resistor in the output line, as shown in figures 18.4 and 18.5. 1. Conditions: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V 2. Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V Rev.3.00 Mar. 26, 2007 Page 541 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics LSI 2 k Port Darlington pair Figure 18.4 Darlington Pair Drive Circuit (Example) LSI Ports 600 LED Figure 18.5 LED Drive Circuit (Example) Rev.3.00 Mar. 26, 2007 Page 542 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.2.3 AC Characteristics Bus timing parameters are listed in table 18.11. Control signal timing parameters are listed in table 18.12. Timing parameters of the on-chip supporting modules are listed in table 18.13. Table 18.11 Bus Timing Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 10 MHz Item Clock cycle time Clock low pulse width Clock high pulse width Clock rise time Clock fall time Address delay time Address hold time Address strobe delay time Write strobe delay time Strobe delay time Write data strobe pulse width 1 Write data strobe pulse width 2 Address setup time 1 Address setup time 2 Read data setup time Read data hold time Symbol tcyc tCL tCH tCr tCf tAD tAH tASD tWSD tSD tWSW1* tWSW2* tAS1 tAS2 tRDS tRDH Min 100 30 30 -- -- -- 20 -- -- -- 60 110 15 65 35 0 Max 500 -- -- 15 15 50 -- 40 50 50 -- -- -- -- -- -- Condition B 18 MHz Min 55.5 17 17 -- -- -- 10 -- -- -- 32 62 10 38 15 0 Max 500 -- -- 10 10 25 -- 25 25 25 -- -- -- -- -- -- Unit ns Test Conditions Figure 18.7, Figure 18.8 Rev.3.00 Mar. 26, 2007 Page 543 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Condition A 10 MHz Item Write data delay time Write data setup time 1 Write data setup time 2 Write data hold time Read data access time 1 Read data access time 2 Read data access time 3 Read data access time 4 Precharge time Wait setup time Wait hold time Note: * Symbol tWDD tWDS1 tWDS2 tWDH tACC1* tACC2* tACC3* tACC4* tPCH* tWTS tWTH Min -- 40 -10 20 -- -- -- -- 60 40 10 Max 75 -- -- -- 100 200 50 150 -- -- -- Condition B 18 MHz Min -- 10 -10 20 -- -- -- -- 40 25 5 Max 55 -- -- -- 50 105 20 80 -- -- -- ns Figure 18.9 Unit ns Test Conditions Figure 18.7, Figure 18.8 For condition A, the following times depend on the clock cycle time as shown below. tWSW1 = 1.0 x tcyc -40 (ns) tACC1 = 1.5 x tcyc -50 (ns) tWSW2 = 1.5 x tcyc -40 (ns) tACC2 = 2.5 x tcyc -50 (ns) tACC3 = 1.0 x tcyc -50 (ns) tPCH = 1.0 x tcyc -40 (ns) tACC4 = 2.0 x tcyc -50 (ns) For condition B, the following times depend on the clock cycle time as shown below. tWSW1 = 1.0 x tcyc -24 (ns) tACC1 = 1.5 x tcyc -34 (ns) tACC2 = 2.5 x tcyc -34 (ns) tWSW2 = 1.5 x tcyc -22 (ns) tPCH = 1.0 x tcyc -21 (ns) tACC3 = 1.0 x tcyc -36 (ns) tACC4 = 2.0 x tcyc -31 (ns) Rev.3.00 Mar. 26, 2007 Page 544 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.12 Control Signal Timing Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 10 MHz Item RES setup time RES pulse width Mode programming setup time NMI setup time (NMI, IRQ0, IRQ1, IRQ4, IRQ5) NMI hold time (NMI, IRQ0, IRQ1, IRQ4, IRQ5) Interrupt pulse width (NMI, IRQ1, IRQ0 when exiting software standby mode) Clock oscillator settling time at reset (crystal) Clock oscillator settling time in software standby (crystal) Symbol tRESS tRESW tMDS tNMIS tNMIH tNMIW Min 200 20 200 200 10 200 Max -- -- -- -- -- -- Condition B 18 MHz Min 200 20 200 150 10 200 Max -- -- -- -- -- -- Unit ns tcyc ns ns Figure 18.12 Test Conditions Figure 18.10 tOSC1 tOSC2 20 8 -- -- 20 7 -- -- ms ms Figure 18.13 Figure 17.1 Rev.3.00 Mar. 26, 2007 Page 545 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.13 Timing of On-Chip Supporting Modules Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 10 MHz Item ITU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges SCI Input clock cycle Asynchronous Synchronous Input clock rise time Input clock fall time Input clock pulse width Transmit data delay time Receive data setup time (synchronous) Receive data hold time (synchronous clock input) Receive data hold time (synchronous clock output) tSCKr tSCKf tSCKW tTXD tRXS tRXH Symbol tTOCD tTICS tTCKS tTCKWH tTCKWL tScyc Min -- 50 50 1.5 2.5 4 6 -- -- 0.4 -- 100 100 Max 100 -- -- -- -- -- -- 1.5 1.5 0.6 100 -- -- Condition B 18 MHz Min -- 50 50 1.5 2.5 4 6 -- -- 0.4 -- 100 100 Max 100 -- -- -- -- -- -- 1.5 1.5 0.6 100 -- -- tScyc ns Figure 18.18 Figure 18.17 tcyc Figure 18.16 Unit ns Test Conditions Figure 18.15 0 -- 0 -- Rev.3.00 Mar. 26, 2007 Page 546 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Condition A 10 MHz Item Ports and TPC Output data delay time Input data setup time Input data hold time Symbol tPWD tPRS tPRH Min -- 50 50 Max 100 -- -- Condition B 18 MHz Min -- 50 50 Max 100 -- -- Unit ns Test Conditions Figure 18.14 5V C = 90 pF: ports 1, 2, 3, 5, 6, 8, RL This LSI output pin C = 30 pF: ports 9, A, B R L = 2.4 k R H = 12 k C RH Input/output timing measurement levels * Low: 0.8 V * High: 2.0 V Figure 18.6 Output Load Circuit Rev.3.00 Mar. 26, 2007 Page 547 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.2.4 A/D Conversion Characteristics Table 18.14 lists the A/D conversion characteristics. Table 18.14 A/D Converter Characteristics Condition A: VCC = 3.0 V to 5.5 V, AVCC = 3.0 V to 5.5 V, VSS = AVSS = 0 V, = 2 MHz to 10 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (widerange specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, VSS = AVSS = 0 V, = 2 MHz to 18 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Condition A 10 MHz Item Resolution Conversion time Analog input capacitance Permissible signalsource impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 -- -- -- Typ 10 -- -- -- Max 10 13.4 20 5* 1 Condition B 18 MHz Min 10 -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 7.5 20 10* 5* 3 2 Unit bits s pF k -- -- -- -- -- -- -- -- -- -- 7.5 7.5 7.5 0.5 8.0 -- -- -- -- -- 3.5 3.5 3.5 0.5 4.0 LSB LSB LSB LSB LSB Notes: 1. The value is for = 10 MHz. 2. The value is for 12 MHz. 3. The value is for > 12 MHz. Rev.3.00 Mar. 26, 2007 Page 548 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.2.5 Flash Memory Characteristics Table 18.15 shows the flash memory characteristics. Table 18.15 Flash Memory Characteristics (1) Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V Ta = 0C to +75C (program/erase operating temperature range: regular specifications), Ta = 0C to +85C (program/erase operating temperature range: wide-range specifications) Test condition Item Programming time*1 *2 *4 Erase time* * * 1 3 5 Symbol tP tE NWEC 1 Min -- -- -- 10 50 150 10 10 4 2 4 -- 10 200 5 10 10 20 2 5 30 Typ 10 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 200 300 100 -- -- 500 -- -- -- -- -- 403 -- -- 10 -- -- -- -- -- 60 Unit ms/32 bytes ms/block Times s s s s s s s s Times s s ms s s s s s Times Reprogramming count Programming Wait time after SWE bit setting* Wait time after PSU bit setting* Wait time after P bit setting*1 *4 Wait time after P bit clear*1 Wait time after PSU bit clear* 1 x y z 1 1 Wait time after PV bit setting* 1 Wait time after H'FF dummy write* Wait time after PV bit clear* 1 Maximum programming count* * Erase Wait time after SWE bit setting* 1 1 4 N x y z Wait time after ESU bit setting*1 Wait time after E bit setting* * Wait time after E bit clear* 1 1 5 Wait time after ESU bit clear* 1 1 Wait time after EV bit setting* 1 Wait time after H'FF dummy write* Wait time after EV bit clear* Maximum erase count* * 1 5 1 N Notes: 1. Set the times according to the program/erase algorithms. 2. Programming time per 32 bytes (Shows the total time the flash memory control register (FLMCR) is set. It does not include the programming verification time.) Rev.3.00 Mar. 26, 2007 Page 549 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 3. Block erase time (Shows the period the E bit in FLMCR is set. It does not include the erase verification time.) 4. To specify the maximum programming time (tP(max)) in the 32-byte programming flowchart, set the max value (403) for the maximum programming count (N). The wait time after P bit setting (z) should be changed as follows according to the programming counter value. Programming counter value of 1 to 4: z = 150 s Programming counter value of 5 to 403: z = 500 s 5. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum erase count (N): tE(max) = Wait time after E bit setting (z) x maximum erase count (N) To set the maximum erase time, the values of z and N should be set so as to satisfy the above formula. Examples: When z = 5 [ms]: N = 60 times When z = 10 [ms]: N = 30 times Rev.3.00 Mar. 26, 2007 Page 550 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics Table 18.15 Flash Memory Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, VSS = AVSS = 0 V Ta = 0C to +75C (Programming/erasing operating temperature range: regular specification) Ta = 0C to +85C (Programming/erasing operating temperature range: wide-range specification) Test condition Item Programming time*1 *2 *4 Erase time* * * 1 3 5 Symbol tP tE NWEC 1 Min -- -- -- 10 50 150 10 10 4 2 4 -- 10 200 5 10 10 20 2 5 30 Typ 10 100 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max 200 300 100 -- -- 500 -- -- -- -- -- 403 -- -- 10 -- -- -- -- -- 60 Unit ms/32 bytes ms/block Times s s s s s s s s Times s s ms s s s s s Times Reprogramming count Programming Wait time after SWE bit setting* Wait time after PSU bit setting* Wait time after P bit setting*1 *4 Wait time after P bit clear*1 Wait time after PSU bit clear* 1 x y z 1 1 Wait time after PV bit setting* 1 Wait time after H'FF dummy write* Wait time after PV bit clear* 1 Maximum programming count* * Erase Wait time after SWE bit setting* 1 1, 4 N x y z Wait time after ESU bit setting*1 Wait time after E bit setting* * Wait time after E bit clear* 1 1 5 Wait time after ESU bit clear* 1 1 Wait time after EV bit setting* 1 Wait time after H'FF dummy write* Wait time after EV bit clear* Maximum erase count* * 1 5 1 N Notes: 1. Make each time setting in accordance with the program/program-verify flowchart or erase/erase-verify flowchart. 2. Programming time per 32 bytes (Shows the total period for which the P-bit in the flash memory control register (FLMCR) is set. It does not include the programming verification time.) 3. Block erase time (Shows the total period for which the E-bit in FLMCR is set. It does not include the erase verification time.) Rev.3.00 Mar. 26, 2007 Page 551 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 4. To specify the maximum programming time (tP(max)) in the 32-byte programming flowchart, set the maximum value (403) for the maximum programming count (N). The wait time after P bit setting (z) should be changed as follows according to the programming counter value. Programming counter value of 1 to 4: z = 150 s Programming counter value of 5 to 403: z = 500 s 5. For the maximum erase time (tE(max)), the following relationship applies between the wait time after E bit setting (z) and the maximum erase count (N): tE(max) = Wait time after E bit setting (z) x maximum erase count (N) To set the maximum erase time, the values of z and N should be set so as to satisfy the above formula. Examples: When z = 5 [ms], N = 60 times When z = 10 [ms], N = 30 times 18.3 Operational Timing This section shows timing diagrams. 18.3.1 Bus Timing Bus timing is shown as follows: * Basic bus cycle: two-state access Figure 18.7 shows the timing of the external two-state access cycle. * Basic bus cycle: three-state access Figure 18.8 shows the timing of the external three-state access cycle. * Basic bus cycle: three-state access with one wait state Figure 18.9 shows the timing of the external three-state access cycle with one wait state inserted. Rev.3.00 Mar. 26, 2007 Page 552 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics T1 tcyc tCH tCf tAD A23 to A 0 tCr tCL T2 tPCH tASD AS tAS1 tPCH tASD RD (read) tAS1 tACC1 D7 to D0 (read) tASD WR (write) tAS1 tWSW1 tWDD D7 to D0 (write) tWDS1 tWDH tSD tAH tRDS tRDH tACC3 tSD tAH tACC3 tSD tAH tPCH Figure 18.7 Basic Bus Cycle: Two-State Access Rev.3.00 Mar. 26, 2007 Page 553 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics T1 A23 to A0 T2 T3 tACC4 AS tACC4 RD (read) tACC2 D7 to D0 (read) tWSD WR (write) tAS2 tWDS2 D7 to D0 (write) tWSW2 tRDS Figure 18.8 Basic Bus Cycle: Three-State Access Rev.3.00 Mar. 26, 2007 Page 554 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics T1 A23 to A0 AS RD (read) D7 to D0 (read) T2 TW T3 WR (write) D7 to D0 (write) tWTS WAIT tWTH tWTS tWTH Figure 18.9 Basic Bus Cycle: Three-State Access with One Wait State Rev.3.00 Mar. 26, 2007 Page 555 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.3.2 Control Signal Timing Control signal timing is shown as follows: * Reset input timing Figure 18.10 shows the reset input timing. * Reset output timing Figure 18.11 shows the reset output timing. * Interrupt input timing Figure 18.12 shows the interrupt input timing for NMI and IRQ5, IRQ4, IRQ1, and IRQ0. tRESS RES tMDS MD2 to MD0 FWE* Note: * The FWE input timing shown is for entering and exiting boot mode. tRESW tRESS Figure 18.10 Reset Input Timing tRESD RESO* tRESOW Note: * Flash version does not have RESO output pin tRESD Figure 18.11 Reset Output Timing Rev.3.00 Mar. 26, 2007 Page 556 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics tNMIS NMI tNMIS IRQ E tNMIS IRQ L IRQ E : Edge-sensitive IRQ i IRQ L : Level-sensitive IRQ i (i = 0, 1, 4, and 5) tNMIW NMI IRQ j (j = 0, 1) tNMIH tNMIH Figure 18.12 Interrupt Input Timing Rev.3.00 Mar. 26, 2007 Page 557 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.3.3 Clock Timing Clock timing is shown below. * Oscillator settling timing Figure 18.13 shows the oscillator settling timing. VCC STBY tOSC1 RES tOSC1 Figure 18.13 Oscillator Settling Timing 18.3.4 TPC and I/O Port Timing TPC and I/O port timing is shown below. T1 tPRS Ports 1 to 3, 5 to 9, A, and B (read) Ports 1 to 3, 5, 6, 8, 9, A, and B (write) tPRH T2 T3 tPWD Figure 18.14 TPC and I/O Port Input/Output Timing Rev.3.00 Mar. 26, 2007 Page 558 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.3.5 ITU Timing ITU timing is shown as follows: * ITU input/output timing Figure 18.15 shows the ITU input/output timing. * ITU external clock input timing Figure 18.16 shows the ITU external clock input timing. tTOCD Output compare*1 tTICS Input capture*2 Notes: 1. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4, TOCXA4, TOCXB4 2. TIOCA0 to TIOCA4, TIOCB0 to TIOCB4 Figure 18.15 ITU Input/Output Timing tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 18.16 ITU External Clock Input Timing Rev.3.00 Mar. 26, 2007 Page 559 of 682 REJ09B0353-0300 Section 18 Electrical Characteristics 18.3.6 SCI Input/Output Timing SCI timing is shown as follows: * SCI input clock timing Figure 18.17 shows the SCI input clock timing. * SCI input/output timing (synchronous mode) Figure 18.18 shows the SCI input/output timing in synchronous mode. tSCKr tSCKf tSCKW SCK tScyc Figure 18.17 SCK Input Clock Timing tScyc SCK tTXD TxD (transmit data) RxD (receive data) tRXS tRXH Figure 18.18 SCI Input/Output Timing in Synchronous Mode Rev.3.00 Mar. 26, 2007 Page 560 of 682 REJ09B0353-0300 Appendix A Instruction Set Appendix A Instruction Set A.1 Instruction List Operand Notation Symbol Rd Rs Rn ERd ERs ERn (EAd) (EAs) PC SP CCR N Z V C disp + - x / * ( ), < > Note: * Description General destination register* General source register* General register* General destination register (address register or 32-bit register) General source register (address register or 32-bit register) General register (32-bit register) Destination operand Source operand Program counter Stack pointer Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Displacement Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Addition of the operands on both sides Subtraction of the operand on the right from the operand on the left Multiplication of the operands on both sides Division of the operand on the left by the operand on the right Logical AND of the operands on both sides Logical OR of the operands on both sides Exclusive logical OR of the operands on both sides NOT (logical complement) Contents of operand General registers include 8-bit registers (R0H to R7H and R0L to R7L) and 16-bit registers (R0 to R7 and E0 to E7). Rev.3.00 Mar. 26, 2007 Page 561 of 682 REJ09B0353-0300 Appendix A Instruction Set Condition Code Notation Symbol Description Changed according to execution result Undetermined (no guaranteed value) Cleared to 0 Set to 1 Not affected by execution of the instruction Varies depending on conditions, described in notes * 0 1 -- Rev.3.00 Mar. 26, 2007 Page 562 of 682 REJ09B0353-0300 Appendix A Instruction Set Table A.1 Instruction Set 1. Data transfer instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd Operation #xx:8 Rd8 Rs8 Rd8 @ERs Rd8 @(d:16, ERs) Rd8 @(d:24, ERs) Rd8 @ERs RD8 ERs32+1 ERs32 @aa:8 Rd8 @aa:16 Rd8 @aa:24 Rd8 Rs8 @ERd Rd8 @(d:16, ERd) Rd8 @(d:24, ERd) ERd32-1 ERd32 Rs8 @ERd Rs8 @aa:8 Rs8 @aa:16 Rs8 @aa:24 @aa Condition Code I HN Z V C B B B B 2 2 2 4 ---- ---- ---- ---- 0-- 0-- 0-- 0-- 2 2 4 6 B 8 ---- 0-- 10 B 2 ---- 0-- 6 MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd B B B B B 2 4 6 2 4 ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 6 B 8 ---- 0-- 10 B 2 ---- 0-- 6 MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd B B B 2 4 6 4 2 2 4 ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 4 6 8 4 2 4 6 W #xx:16 Rd16 W Rs16 Rd16 W @ERs Rd16 W @(d:16, ERs) Rd16 W @(d:24, ERs) Rd16 W @ERs Rd16 ERs32+2 @ERd32 W @aa:16 Rd16 8 ---- 0-- 10 2 ---- 0-- 6 MOV.W @aa:16, Rd 4 ---- 0-- 6 Rev.3.00 Mar. 26, 2007 Page 563 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @-ERd Operation @aa Condition Code I HN Z V C W @aa:24 Rd16 W Rs16 @ERd W Rs16 @(d:16, ERd) W Rs16 @(d:24, ERd) W ERd32-2 ERd32 Rs16 @ERd W Rs16 @aa:16 W Rs16 @aa:24 L L L L #xx:32 Rd32 ERs32 ERd32 @ERs ERd32 @(d:16, ERs) ERd32 @(d:24, ERs) ERd32 @ERs ERd32 ERs32+4 ERs32 @aa:16 ERd32 @aa:24 ERd32 ERs32 @ERd ERs32 @(d:16, ERd) ERs32 @(d:24, ERd) ERd32-4 ERd32 ERs32 @ERd ERs32 @aa:16 ERs32 @aa:24 4 6 6 2 4 6 2 4 6 ---- ---- ---- 0-- 0-- 0-- 8 4 6 8 ---- 0-- 8 2 ---- 0-- 6 MOV.W Rs, @aa:16 MOV.W Rs, @aa:24 MOV.L #xx:32, Rd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd 4 6 ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 6 8 6 2 8 10 L 10 ---- 0-- 14 L 4 ---- 0-- 10 MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd L L L L 6 8 ---- ---- ---- ---- 0-- 0-- 0-- 0-- 10 12 8 10 L 10 ---- 0-- 14 L 4 ---- 0-- 10 MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 POP.W Rn L L 6 8 ---- ---- 2 ---- 0-- 0-- 0-- 10 12 6 W @SP Rn16 SP+2 SP L @SP ERn32 SP+4 SP POP.L ERn 4 ---- 0-- 10 Rev.3.00 Mar. 26, 2007 Page 564 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic PUSH.W Rn Operation @aa Condition Code I HN Z V C W SP-2 SP Rn16 @SP L SP-4 SP ERn32 @SP Cannot be used in the H8/3039 Group Cannot be used in the H8/3039 Group 4 2 ---- 0-- 6 PUSH.L ERn 4 ---- 0-- 10 MOVFPE @aa:16, Rd MOVTPE Rs, @aa:16 B Cannot be used in the H8/3039 Group Cannot be used in the H8/3039 Group B 4 Rev.3.00 Mar. 26, 2007 Page 565 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set 2. Arithmetic instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) @aa Condition Code I -- HN Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd Operation Rd8+#xx:8 Rd8 Rd8+Rs8 Rd8 Z V C B B 2 2 4 2 6 2 2 4 2 6 -- W Rd16+#xx:16 Rd16 W Rd16+Rs16 Rd16 L ERd32+#xx:32 ERd32 ERd32+ERs32 ERd32 Rd8+#xx:8 +C Rd8 Rd8+Rs8 +C Rd8 ERd32+1 ERd32 ERd32+2 ERd32 ERd32+4 ERd32 Rd8+1 Rd8 -- (1) -- (1) -- (2) ADD.L ERs, ERd L 2 -- (2) 2 ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.L #1, ERd ADDS.L #2, ERd ADDS.L #4, ERd INC.B Rd INC.W #1, Rd INC.W #2, Rd B B L L L B 2 2 2 2 2 2 2 2 -- -- (3) (3) 2 2 2 2 2 2 2 2 ------------ ------------ ------------ ---- ---- ---- -- -- -- W Rd16+1 Rd16 W Rd16+2 Rd16 Rev.3.00 Mar. 26, 2007 Page 566 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic INC.L #1, ERd INC.L #2, ERd DAA Rd Operation ERd32+1 ERd32 ERd32+2 ERd32 Rd8 decimal adjust Rd8 Rd8-Rs8 Rd8 @aa Condition Code I HN Z V C -- -- L L B 2 2 2 ---- ---- --* 2 2 2 *-- SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd B 2 4 2 6 -- 2 4 2 6 -- (1) -- (1) -- (2) W Rd16-Rs16 Rd16 L ERd32-#xx:32 ERd32 ERd32-ERs32 ERd32 Rd8-#xx:8-C Rd8 Rd8-Rs8-C Rd8 ERd32-1 ERd32 ERd32-2 ERd32 ERd32-4 ERd32 Rd8-1 Rd8 2 SUB.L ERs, ERd L 2 -- (2) W Rd16-#xx:16 Rd16 2 SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.L #1, ERd SUBS.L #2, ERd SUBS.L #4, ERd DEC.B Rd DEC.W #1, Rd DEC.W #2, Rd DEC.L #1, ERd DEC.L #2, ERd DAS.Rd B B L L L B -- 2 2 2 2 2 2 2 2 2 2 -- (3) (3) 2 2 2 2 2 2 2 2 2 2 2 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* W Rd16-1 Rd16 W Rd16-2 Rd16 L L B ERd32-1 ERd32 ERd32-2 ERd32 Rd8 decimal adjust Rd8 Rd8 x Rs8 Rd16 (unsigned multiplication) *-- MULXU. B Rs, Rd B 2 ------------ -- -- -- -- -- 14 MULXU. W Rs, ERd W Rd16 x Rs16 ERd32 (unsigned multiplication) B Rd8 x Rs8 Rd16 (signed multiplication) 2 ------------ 22 MULXS. B Rs, Rd 4 ---- ---- 16 MULXS. W Rs, ERd W Rd16 x Rs16 ERd32 (signed multiplication) B Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (unsigned division) 4 ---- ---- 24 DIVXU. B Rs, Rd 2 -- -- (6) (7) -- -- 14 Rev.3.00 Mar. 26, 2007 Page 567 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic DIVXU. W Rs, ERd Operation @aa Condition Code I HN Z V C W ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (unsigned division) B Rd16 / Rs8 Rd16 (RdH: remainder, RdL: quotient) (signed division) 2 -- -- (6) (7) -- -- 22 DIVXS. B Rs, Rd 4 -- -- (8) (7) -- -- 16 DIVXS. W Rs, ERd W ERd32 / Rs16 ERd32 (Ed: remainder, Rd: quotient) (signed division) B B Rd8-#xx:8 Rd8-Rs8 4 2 4 -- -- (8) (7) -- -- 24 CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd NEG.B Rd NEG.W Rd NEG.L ERd EXTU.W Rd -- 2 -- 2 2 4 2 4 2 2 2 2 2 W Rd16-#xx:16 W Rd16-Rs16 L L B ERd32-#xx:32 ERd32-ERs32 0-Rd8 Rd8 -- (1) 2 -- (1) -- (2) 2 2 2 2 2 -- (2) -- -- -- 6 W 0-Rd16 Rd16 L 0-ERd32 ERd32 W 0 ( ---- 0 0-- EXTU.L ERd 2 ---- 0 0-- 2 EXTS.W Rd W ( 2 ---- 0-- 2 EXTS.L ERd 2 ---- 0-- 2 Rev.3.00 Mar. 26, 2007 Page 568 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set 3. Logic instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd NOT.B Rd NOT.W Rd NOT.L ERd Operation Rd8#xx:8 Rd8 Rd8Rs8 Rd8 @aa Condition Code I HN Z V C B B 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 2 2 4 2 6 4 2 2 4 2 6 4 2 2 4 2 6 4 2 2 2 W Rd16#xx:16 Rd16 W Rd16Rs16 Rd16 L L B B ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 W Rd16#xx:16 Rd16 W Rd16Rs16 Rd16 L L B B ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8#xx:8 Rd8 Rd8Rs8 Rd8 W Rd16#xx:16 Rd16 W Rd16Rs16 Rd16 L L B ERd32#xx:32 ERd32 ERd32ERs32 ERd32 Rd8 Rd8 W Rd16 Rd16 L Rd32 Rd32 Rev.3.00 Mar. 26, 2007 Page 569 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set 4. Shift instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR.B Rd SHLR.W Rd SHLR.L ERd ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR.B Rd ROTR.W Rd ROTR.L ERd Operation @aa Condition Code I HN Z V C B W L B W L B W L B W L B W L B W L B W L B W L 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 C MSB LSB 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSB LSB C 2 2 0 C MSB LSB 2 2 2 0 MSB LSB C 2 2 2 2 C MSB LSB 2 2 2 MSB LSB C 2 2 2 C MSB LSB 2 2 2 MSB LSB C 2 Rev.3.00 Mar. 26, 2007 Page 570 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set 5. Bit manipulation instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BNOT #xx:3, Rd Operation (#xx:3 of Rd8) 1 (#xx:3 of @ERd) 1 (#xx:3 of @aa:8) 1 (Rn8 of Rd8) 1 (Rn8 of @ERd) 1 (Rn8 of @aa:8) 1 (#xx:3 of Rd8) 0 (#xx:3 of @ERd) 0 (#xx:3 of @aa:8) 0 (Rn8 of Rd8) 0 (Rn8 of @ERd) 0 (Rn8 of @aa:8) 0 (#xx:3 of Rd8) (#xx:3 of Rd8) (#xx:3 of @ERd) (#xx:3 of @ERd) (#xx:3 of @aa:8) (#xx:3 of @aa:8) (Rn8 of Rd8) (Rn8 of Rd8) (Rn8 of @ERd) (Rn8 of @ERd) (Rn8 of @aa:8) (Rn8 of @aa:8) (#xx:3 of Rd8) Z (#xx:3 of @ERd) Z (#xx:3 of @aa:8) Z (Rn8 of @Rd8) Z (Rn8 of @ERd) Z (Rn8 of @aa:8) Z (#xx:3 of Rd8) C @aa Condition Code I HN Z V C B B B B B B B B B B B B B 2 4 4 2 4 4 2 4 4 2 4 4 2 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 8 8 2 8 8 2 8 8 2 8 8 2 BNOT #xx:3, @ERd B 4 ------------ 8 BNOT #xx:3, @aa:8 B 4 ------------ 8 BNOT Rn, Rd B 2 ------------ 2 BNOT Rn, @ERd B 4 ------------ 8 BNOT Rn, @aa:8 B 4 ------------ 8 BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BLD #xx:3, Rd B B B B B B B 2 4 4 2 4 4 2 ------ ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- 2 6 6 2 6 6 2 ---------- Rev.3.00 Mar. 26, 2007 Page 571 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) @ERn Condition Code I HN Z V C Mnemonic BLD #xx:3, @ERd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @ERd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 Operation (#xx:3 of @ERd) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd) C (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C (#xx:3 of @ERd24) C (#xx:3 of @aa:8) C (#xx:3 of Rd8) C (#xx:3 of @ERd24) C (#xx:3 of @aa:8) C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C C (#xx:3 of @aa:8) C B B B B B B B B B B B B B B B B B B B B B B B B B B B B B 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 ---------- ---------- ---------- ---------- ---------- 6 6 2 6 6 2 8 8 2 8 8 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- C(#xx:3 of Rd8) C C(#xx:3 of @ERd24) C C(#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C C (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C C (#xx:3 of @aa:8) C C (#xx:3 of Rd8) C C (#xx:3 of @ERd24) C C (#xx:3 of @aa:8) C Rev.3.00 Mar. 26, 2007 Page 572 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @aa #xx Rn Appendix A Instruction Set 6. Branching instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 Operation If condition Always is true then PC PC+d else Never next; CZ=0 @aa Condition Code I HN Z V C -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 2 4 2 4 2 4 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 4 6 CZ=1 2 4 C=0 2 4 C=1 2 4 Z=0 2 4 Z=1 2 4 V=0 2 4 V=1 2 4 N=0 2 4 N=1 2 4 NV=0 2 4 N V=1 Z (N V) =0 2 4 2 4 Rev.3.00 Mar. 26, 2007 Page 573 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set Addressing Mode and Instruction Length (bytes) No. of States*1 Operand Size @-ERn/@ERn+ @(d, ERn) Mnemonic BLE d:8 BLE d:16 Operation If condition is true then PC PC+d else next; Z (N V) =1 @aa Condition Code I HN Z V C -- -- 2 4 ------------ ------------ 4 6 JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 -- PC ERn -- PC aa:24 -- PC @aa:8 -- PC @-SP PC PC+d:8 -- PC @-SP PC PC+d:16 -- PC @-SP PC @ERn -- PC @-SP PC @aa:24 -- PC @-SP PC @aa:8 -- PC @SP+ 2 4 2 2 ------------ ------------ ------------ ------------ 8 6 4 6 10 8 BSR d:16 4 ------------ 8 10 JSR @ERn 2 ------------ 6 JSR @aa:24 4 ------------ 8 10 JSR @@aa:8 2 ------------ 8 12 RTS 2 ------------ 8 10 Rev.3.00 Mar. 26, 2007 Page 574 of 682 REJ09B0353-0300 Advanced 8 @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set 7. System control instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic TRAPA #x:2 Operation @aa Condition Code I HN Z V C -- PC @-SP CCR @-SP 2 1 ---------- 14 16 RTE 10 SLEEP ------------ 2 LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR 2 2 6 8 W @ERs CCR W @(d:16, ERs) CCR W @(d:24, ERs) CCR W @ERs CCR ERs32+2 ERs32 W @aa:16 CCR W @aa:24 CCR B CCR Rd8 2 10 12 4 8 LDC @aa:16, CCR LDC @aa:24, CCR STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd 6 8 8 10 2 6 8 ------------ 4 6 ------------ ------------ W CCR @ERd W CCR @(d:16, ERd) W CCR @(d:24, ERd) W ERd32-2 ERd32 CCR @ERd W CCR @aa:16 W CCR @aa:24 B B B CCR#xx:8 CCR CCR#xx:8 CCR CCR#xx:8 CCR 2 2 2 10 ------------ 12 4 ------------ 8 STC CCR, @aa:16 STC CCR, @aa:24 ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP 6 8 ------------ ------------ 8 10 2 2 2 2 -- PC PC+2 2 ------------ Rev.3.00 Mar. 26, 2007 Page 575 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn Appendix A Instruction Set 8. Block transfer instructions Addressing Mode and Instruction Length (bytes) @-ERn/@ERn+ No. of States*1 Operand Size @(d, ERn) Mnemonic EEPMOV. B Operation @aa Condition Code I HN Z V C -- if R4L 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L until R4L=0 else next -- if R4 0 then repeat @R5 @R6 R5+1 R5 R6+1 R6 R4-1 R4 until R4=0 else next 4 ------------ 8+4n*2 EEPMOV. W 4 ------------ 8+4n*2 Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. For other cases see section A.3, Number of States Required for Execution. 2. n is the value set in register R4L or R4. (1) (2) (3) (4) (5) Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. Retains its previous value when the result is zero; otherwise cleared to 0. Set to 1 when the adjustment produces a carry; otherwise retains its previous value. The number of states required for execution of an instruction that transfers data in synchronization with the E clock is variable. (6) Set to 1 when the divisor is negative; otherwise cleared to 0. (7) Set to 1 when the divisor is zero; otherwise cleared to 0. (8) Set to 1 when the quotient is negative; otherwise cleared to 0. Rev.3.00 Mar. 26, 2007 Page 576 of 682 REJ09B0353-0300 Advanced @(d, PC) Implied Normal @@aa @ERn #xx Rn A.2 Instruction code: Instruction when most significant bit of BH is 1. 4 ORC ADD SUB Table A.2 Table A.2 (2) (2) CMP SUBX MOV OR.B XOR.B AND.B Table A.2 (2) XORC ANDC LDC Table A.2 Table A.2 (2) (2) ADDX Table A.2 (2) Table A.2 (2) 5 6 7 8 9 A B C D E F Table A.2 1st byte 2nd byte AH AL BH BL Instruction when most significant bit of BH is 0. 3 LDC AL AH 0 1 2 0 NOP Table A.2 (2) STC 1 Table A.2 Table A.2 Table A.2 Table A.2 (2) (2) (2) (2) 2 MOV.B 3 BLS BVS JMP MOV MOV BIOR ADD ADDX CMP SUBX OR XOR AND MOV BIXOR BIAND BILD Table A.2 Table A.2 EEPMOV (2) (2) Table A.2 (3) BSR BGE DIVXU BST OR BTST BOR BXOR BAND BIST BLD XOR AND RTS BSR RTE TRAPA Table A.2 (2) BCC BCS BNE BEQ BVC BPL BMI BLT BGT JSR BLE Operation Code Maps Operation Code Map (1) 4 BRA BRN BHI 5 MULXU DIVXU MULXU 6 BSET BNOT BCLR 7 8 9 A B C D E Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 577 of 682 REJ09B0353-0300 F Table A.2 Instruction code: 1st byte 2nd byte AH AL BH BL 2 LDC/STC SLEEP ADD INC ADDS MOV SHLL SHAL SHAR ROTL ROTR EXTU NEG EXTU SHAR ROTL ROTR NEG SUB DEC DEC SUB CMP BHI BLS SUB SUB OR XOR OR XOR BCS CMP CMP BCC BNE AND AND BEQ BVC BVS BPL BMI BGE BLT BGT BLE DEC DEC EXTS EXTS SHAL SHLR ROTXL ROTXR NOT INC INC INC Table A.2 Table A.2 (3) (3) 3 4 5 6 7 8 9 A B C D E F Table A.2 (3) BH AH AL 0 1 01 MOV 0A INC Appendix A Instruction Set 0B ADDS 0F DAA Operation Code Map (2) 10 SHLL Rev.3.00 Mar. 26, 2007 Page 578 of 682 REJ09B0353-0300 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC 1B SUBS 1F DAS 58 BRA BRN 79 MOV ADD 7A MOV ADD Instruction code: Instruction when most significant bit of DH is 1. Table A.2 1st byte 2nd byte 3rd byte 4th byte AH AL BH BL CH CL DH DL Instruction when most significant bit of DH is 0. CL 2 3 4 5 6 7 8 9 A B C D E F AH ALBH BLCH LDC STC STC STC MULXS DIVXS OR AND BTST BOR BTST BIOR BCLR BIST BCLR BTST BOR BLD BILD BST BIST BCLR BTST BIOR BCLR BIXOR BIAND BXOR BAND BIXOR BIAND BILD BST BXOR BAND BLD XOR LDC LDC 0 1 01406 LDC STC 01C05 MULXS 01D05 DIVXS Operation Code Map (3) 01F06 7Cr06*1 7Cr07*1 7Dr06*1 BSET BNOT 7Dr07*1 BSET BNOT 7Eaa6*2 7Eaa7*2 7Faa6*2 BSET BNOT 7Faa7*2 BSET BNOT Appendix A Instruction Set Rev.3.00 Mar. 26, 2007 Page 579 of 682 REJ09B0353-0300 Notes: 1. r is the register designation field. 2. aa is the absolute address field. Appendix A Instruction Set A.3 Number of States Required for Execution The tables in this section can be used to calculate the number of states required for instruction execution by the H8/300H CPU. Table A.3 indicates the number of states required per cycle according to the bus size. Table A.4 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. The number of states required for execution of an instruction can be calculated from these two tables as follows: Number of states = I x SI + J x SJ + K x SK + L x SL + M x SM + N x SN Examples of Calculation of Number of States Required for Execution Examples: Advanced mode, stack located in external address space, on-chip supporting modules accessed with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. BSET #0, @FFFFC7:8 From table A.3, SI = 4 and SL = 3 From table A.4, I = L = 2 and J = K = M = N = 0 Number of states = 2 x 4 + 2 x 3 = 14 JSR @@30 From table A.3, SI = SJ = SK = 4 From table A.4, I = J = K = 2 and L = M = N = 0 Number of states = 2 x 4 + 2 x 4 + 2 x 4 = 24 Rev.3.00 Mar. 26, 2007 Page 580 of 682 REJ09B0353-0300 Appendix A Instruction Set Table A.3 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 2-State Access 4 16-Bit Bus 3-State Access 3+m Cycle Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation SI SJ SK SL SM SN On-Chip Memory 2 8-Bit Bus 6 16-Bit Bus 3 3-State 2-State Access Access 6 + 2m 2 3 6 1 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend: m: Number of wait states inserted in external device access Rev.3.00 Mar. 26, 2007 Page 581 of 682 REJ09B0353-0300 Appendix A Instruction Set Table A.4 Number of Cycles per Instruction Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 Word Data Access M Internal Operation N Instruction ADD Mnemonic ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W #xx:16, Rd ADD.W Rs, Rd ADD.L #xx:32, ERd ADD.L ERs, ERd ADDS ADDX ADDS #1/2/4, ERd ADDX #xx:8, Rd ADDX Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd AND.W #xx:16, Rd AND.W Rs, Rd AND.L #xx:32, ERd AND.L ERs, ERd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @ERd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 Rev.3.00 Mar. 26, 2007 Page 582 of 682 REJ09B0353-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 2 2 1 1 1 1 1 1 2 2 2 2 Word Data Access M Internal Operation N 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Instruction Bcc Mnemonic BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3, Rd BCLR #xx:3, @ERd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @ERd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @ERd BIAND #xx:3, @aa:8 BILD BILD #xx:3, Rd BILD #xx:3, @ERd BILD #xx:3, @aa:8 BIOR BIOR #xx:8, Rd BIOR #xx:8, @ERd BIOR #xx:8, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @ERd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @ERd BIXOR #xx:3, @aa:8 Rev.3.00 Mar. 26, 2007 Page 583 of 682 REJ09B0353-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 2 2 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 1 1 1 1 2 2 1 2 1 2 2 2 2 2 2 2 1 1 2 2 2 2 1 1 Word Data Access M Internal Operation N Instruction BLD Mnemonic BLD #xx:3, Rd BLD #xx:3, @ERd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @ERd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @ERd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @ERd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @ERd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @ERd BSET Rn, @aa:8 BSR BSR d:8 Normal Advanced BSR d:16 Normal Advanced BST BST #xx:3, Rd BST #xx:3, @ERd BST #xx:3, @aa:8 BTST BTST #xx:3, Rd BTST #xx:3, @ERd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @ERd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @ERd BXOR #xx:3, @aa:8 Rev.3.00 Mar. 26, 2007 Page 584 of 682 REJ09B0353-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 2 2 1 1 1 1 1 1 1 2 2 Normal Advanced JSR JSR @ERn Normal Advanced JSR @aa:24 Normal Advanced JSR @@aa:8 Normal Advanced 2 2 2 2 2 2 2 2 1 2 1 2 1 2 1 2 1 2 2 2 2 2 2 2n +2*1 2n +2*1 12 20 12 20 Word Data Access M Internal Operation N Instruction CMP Mnemonic CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W #xx:16, Rd CMP.W Rs, Rd CMP.L #xx:32, ERd CMP.L ERs, ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2, Rd DEC.L #1/2, ERd DIVXS DIVXS.B Rs, Rd DIVXS.W Rs, ERd DIVXU DIVXU.B Rs, Rd DIVXU.W Rs, ERd EEPMOV EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2, Rd INC.L #1/2, ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 Rev.3.00 Mar. 26, 2007 Page 585 of 682 REJ09B0353-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 2 3 5 2 3 4 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 2 Word Data Access M Internal Operation N Instruction LDC Mnemonic LDC #xx:8, CCR LDC Rs, CCR LDC @ERs, CCR LDC @(d:16, ERs), CCR LDC @(d:24, ERs), CCR LDC @ERs+, CCR LDC @aa:16, CCR LDC @aa:24, CCR MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @ERs, Rd MOV.B @(d:16, ERs), Rd MOV.B @(d:24, ERs), Rd MOV.B @ERs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B @aa:24, Rd MOV.B Rs, @ERd MOV.B Rs, @(d:16, ERd) MOV.B Rs, @(d:24, ERd) MOV.B Rs, @-ERd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.B Rs, @aa:24 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @ERs, Rd MOV.W @(d:16, ERs), Rd MOV.W @(d:24, ERs), Rd MOV.W @ERs+, Rd MOV.W @aa:16, Rd MOV.W @aa:24, Rd MOV.W Rs, @ERd MOV.W Rs, @(d:16, ERd) MOV.W Rs, @(d:24, ERd) MOV.W Rs, @-ERd MOV.W Rs, @aa:16 Rev.3.00 Mar. 26, 2007 Page 586 of 682 REJ09B0353-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 3 3 1 2 3 5 2 3 4 2 3 5 2 3 4 2 Instruction MOV Mnemonic MOV.W Rs, @aa:24 MOV.L #xx:32, ERd MOV.L ERs, ERd MOV.L @ERs, ERd MOV.L @(d:16, ERs), ERd MOV.L @(d:24, ERs), ERd MOV.L @ERs+, ERd MOV.L @aa:16, ERd MOV.L @aa:24, ERd MOV.L ERs, @ERd MOV.L ERs, @(d:16, ERd) MOV.L ERs, @(d:24, ERd) MOV.L ERs, @-ERd MOV.L ERs, @aa:16 MOV.L ERs, @aa:24 Word Data Access M 1 Internal Operation N 2 2 2 2 2 2 2 2 2 2 2 2 1 1 12 20 12 20 2 2 MOVFPE MOVTPE MULXS MOVFPE @aa:16, Rd* 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 MOVTPE Rs, @aa:16*2 MULXS.B Rs, Rd MULXS.W Rs, ERd MULXU MULXU.B Rs, Rd MULXU.W Rs, ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8, Rd OR.B Rs, Rd OR.W #xx:16, Rd OR.W Rs, Rd OR.L #xx:32, ERd OR.L ERs, ERd Rev.3.00 Mar. 26, 2007 Page 587 of 682 REJ09B0353-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 2 Normal Advanced SHAL SHAL.B Rd SHAL.W Rd SHAL.L ERd SHAR SHAR.B Rd SHAR.W Rd SHAR.L ERd SHLL SHLL.B Rd SHLL.W Rd SHLL.L ERd SHLR SHLR.B Rd SHLR.W Rd SHLR.L ERd SLEEP SLEEP 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 2 2 2 1 2 1 2 2 2 2 2 Word Data Access M Internal Operation N Instruction ORC POP Mnemonic ORC #xx:8, CCR POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.W Rd ROTL.L ERd ROTR ROTR.B Rd ROTR.W Rd ROTR.L ERd ROTXL ROTXL.B Rd ROTXL.W Rd ROTXL.L ERd ROTXR ROTXR.B Rd ROTXR.W Rd ROTXR.L ERd RTE RTS RTE RTS Rev.3.00 Mar. 26, 2007 Page 588 of 682 REJ09B0353-0300 Appendix A Instruction Set Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 2 3 5 2 3 4 1 2 1 3 1 1 1 1 Normal Advanced XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XOR.W #xx:16, Rd XOR.W Rs, Rd XOR.L #xx:32, ERd XOR.L ERs, ERd XORC XORC #xx:8, CCR 2 2 1 1 2 1 3 2 1 1 2 2 2 4 4 1 1 1 1 1 1 2 Word Data Access M Internal Operation N Instruction STC Mnemonic STC CCR, Rd STC CCR, @ERd STC CCR, @(d:16, ERd) STC CCR, @(d:24, ERd) STC CCR, @-ERd STC CCR, @aa:16 STC CCR, @aa:24 SUB SUB.B Rs, Rd SUB.W #xx:16, Rd SUB.W Rs, Rd SUB.L #xx:32, ERd SUB.L ERs, ERd SUBS SUBX SUBS #1/2/4, ERd SUBX #xx:8, Rd SUBX Rs, Rd TRAPA TRAPA #x:2 Notes: 1. n is the value set in register R4L or R4. The source and destination are accessed n+1 times each. 2. Not used with this LSI. Rev.3.00 Mar. 26, 2007 Page 589 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field Appendix B Internal I/O Register Field B.1 Addresses Data Bus Width Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Register (low) Name H'1C H'1D H'1E H'1F H'20 H'21 H'22 H'23 H'24 H'25 H'26 H'27 H'28 H'29 H'2A H'2B H'2C H'2D H'2E H'2F H'30 H'31 H'32 H'33 H'34 H'35 H'36 H'37 H'38 H'39 H'3A H'3B H'3C H'3D H'3E H'3F -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev.3.00 Mar. 26, 2007 Page 590 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field Data Bus Width 8 8 Bit Names Bit 7 FWE -- EB7 -- -- -- -- 8 -- -- -- -- -- -- 8 FLER -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 8 -- PSTOP -- Bit 6 SWE -- EB6 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 ESU -- EB5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 4 PSU -- EB4 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 3 EV -- EB3 -- -- -- -- RAMS -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 2 PV -- EB2 -- -- -- -- RAM2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 1 E -- EB1 -- -- -- -- RAM1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DIV1 -- -- Bit 0 P -- EB0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DIV0 MSTOP0 -- System control Module Name Flash memory Address Register (low) Name H'40 H'41 H'42 H'43 H'44 H'45 H'46 H'47 H'48 H'49 H'4A H'4B H'4C H'4D H'4E H'4F H'50 H'51 H'52 H'53 H'54 H'55 H'56 H'57 H'58 H'59 H'5A H'5B H'5C H'5D H'5E H'5F FLMCR -- EBR -- -- -- -- RAMCR -- -- -- -- -- FLMSR -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- DIVCR MSTCR -- MSTOP5 MSTOP4 MSTOP3 -- Rev.3.00 Mar. 26, 2007 Page 591 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field Data Bus Width 8 8 8 8 8 8 8 8 16 16 16 8 8 8 8 16 16 16 8 8 8 8 16 16 16 -- -- -- -- CCLR1 IOB2 -- -- CCLR0 IOB1 -- -- CKEG1 IOB0 -- -- CKEG0 -- -- -- TPSC2 IOA2 OVIE OVF TPSC1 IOA1 IMIEB IMFB TPSC0 IOA0 IMIEA IMFA ITU channel 2 -- -- -- -- CCLR1 IOB2 -- -- CCLR0 IOB1 -- -- CKEG1 IOB0 -- -- CKEG0 -- -- -- TPSC2 IOA2 OVIE OVF TPSC1 IOA1 IMIEB IMFB TPSC0 IOA0 IMIEA IMFA ITU channel 1 -- -- -- -- -- Bit Names Bit 7 -- -- Bit 6 -- -- MDF -- CCLR1 IOB2 -- -- Bit 5 -- -- FDIR CMD1 CCLR0 IOB1 -- -- Bit 4 STR4 SYNC4 PWM4 CMD0 CKEG1 IOB0 -- -- Bit 3 STR3 SYNC3 PWM3 BFB4 CKEG0 -- -- -- Bit 2 STR2 SYNC2 PWM2 BFA4 TPSC2 IOA2 OVIE OVF Bit 1 STR1 SYNC1 PWM1 BFB3 TPSC1 IOA1 IMIEB IMFB Bit 0 STR0 SYNC0 PWM0 BFA3 TPSC0 IOA0 IMIEA IMFA ITU channel 0 Module Name ITU (all channels) Address Register (low) Name H'60 H'61 H'62 H'63 H'64 H'65 H'66 H'67 H'68 H'69 H'6A H'6B H'6C H'6D H'6E H'6F H'70 H'71 H'72 H'73 H'74 H'75 H'76 H'77 H'78 H'79 H'7A H'7B H'7C H'7D H'7E H'7F H'80 H'81 TSTR TSNC TMDR TFCR TCR0 TIOR0 TIER0 TSR0 TCNT0H TCNT0L GRA0H GRA0L GRB0H GRB0L TCR1 TIOR1 TIER1 TSR1 TCNT1H TCNT1L GRA1H GRA1L GRB1H GRB1L TCR2 TIOR2 TIER2 TSR2 TCNT2H TCNT2L GRA2H GRA2L GRB2H GRB2L Rev.3.00 Mar. 26, 2007 Page 592 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field Data Bus Width 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 16 16 16 16 16 -- -- -- -- -- -- -- -- CCLR1 IOB2 -- -- EXB4 -- CCLR0 IOB1 -- -- EXA4 XTGD CKEG1 IOB0 -- -- EB3 -- CKEG0 -- -- -- EB4 -- TPSC2 IOA2 OVIE OVF EA4 OLS4 TPSC1 IOA1 IMIEB IMFB EA3 OLS3 TPSC0 IOA0 IMIEA IMFA ITU (all channel) ITU channel 4 Bit Names Bit 7 -- -- -- -- Bit 6 CCLR1 IOB2 -- -- Bit 5 CCLR0 IOB1 -- -- Bit 4 CKEG1 IOB0 -- -- Bit 3 CKEG0 -- -- -- Bit 2 TPSC2 IOA2 OVIE OVF Bit 1 TPSC1 IOA1 IMIEB IMFB Bit 0 TPSC0 IOA0 IMIEA IMFA Module Name ITU channel 3 Address Register (low) Name H'82 H'83 H'84 H'85 H'86 H'87 H'88 H'89 H'8A H'8B H'8C H'8D H'8E H'8F H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 H'9A H'9B H'9C H'9D H'9E H'9F TCR3 TIOR3 TIER3 TSR3 TCNT3H TCNT3L GRA3H GRA3L GRB3H GRB3L BRA3H BRA3L BRB3H BRB3L TOER TOCR TCR4 TIOR4 TIER4 TSR4 TCNT4H TCNT4L GRA4H GRA4L GRB4H GRB4L BRA4H BRA4L BRB4H BRB4L Rev.3.00 Mar. 26, 2007 Page 593 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field Data Bus Width 8 8 8 8 8 8 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF SMR BRR SCR TDR SSR RDR -- -- 8 8 8 8 8 8 C/A -- TIE -- TDRE -- -- -- CHR -- RIE -- RDRF -- -- -- PE -- TE -- ORER -- -- -- O/E -- RE -- FER -- -- -- STOP -- MPIE -- PER -- -- -- MP -- TEIE -- TEND -- -- -- CKS1 -- CKE1 -- MPB -- -- -- CKS0 -- CKE0 -- MPBT -- -- -- SCI1 NDRA* NDRB* NDRA* TCSR* TCNT* -- RSTCSR* 8 -- -- -- -- SMR BRR SCR TDR SSR RDR SCMR 8 8 8 8 8 8 8 -- -- -- -- SDIR SINV -- SMIF Smart card interface TDRE RDRF ORER FER PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 2 1 Bit Names Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Register (low) Name H'A0 H'A1 H'A2 H'A3 H'A4 TPMR TPCR NDERB NDERA NDRB* 1 G3NOV G2NOV G1NOV G0NOV TPC NDER8 NDER0 NDR8 -- NDR0 -- -- NDR8 -- NDR0 CKS0 -- -- -- -- -- -- CKS0 SCI0 WDT G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER7 NDR15 NDR15 NDR7 NDR7 -- -- -- -- OVF -- WRST -- -- -- -- C/A NDER6 NDR14 NDR14 NDR6 NDR6 -- -- -- -- WT/IT -- RSTOE -- -- -- -- CHR NDER5 NDR13 NDR13 NDR5 NDR5 -- -- -- -- TME -- -- -- -- -- -- PE NDER4 NDR12 NDR12 NDR4 NDR4 -- -- -- -- -- -- -- -- -- -- -- O/E NDER3 NDR11 -- NDR3 -- -- NDR11 -- NDR3 -- -- -- -- -- -- -- STOP NDER2 NDR10 -- NDR2 -- -- NDR10 -- NDR2 CKS2 -- -- -- -- -- -- MP NDER1 NDR9 -- NDR1 -- -- NDR9 -- NDR1 CKS1 -- -- -- -- -- -- CKS1 8 8 8 8 8 8 8 8 1 1 2 2 Rev.3.00 Mar. 26, 2007 Page 594 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Register (low) Name H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF P1DDR P2DDR P1DR P2DR P3DDR -- P3DR -- P5DDR P6DDR P5DR P6DR -- P8DDR P7DR P8DR P9DDR PADDR P9DR PADR PBDDR -- PBDR -- P2PCR -- -- P5PCR -- -- -- -- P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2 P17 P27 -- P37 -- -- -- -- -- -- -- P77 -- -- -- PA7 -- PB7 -- -- -- P16 P26 -- P36 -- -- -- -- -- -- -- P76 -- -- -- PA6 -- -- -- -- -- -- -- -- -- -- P15 P25 -- P35 -- -- -- P65 -- -- P75 -- P14 P24 -- P34 -- -- -- P64 -- -- P74 -- P13 P23 -- P33 -- P12 P22 -- P32 -- P11 P21 -- P31 -- -- P51 -- -- P71 P81 P10 P20 -- P30 -- P60DDR Port 6 P50 P60 -- P70 P80 Port 7 Port 8 Port 5 Port 6 Port 3 Port 1 Port 2 P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3 P53DDR P52DDR P51DDR P50DDR Port 5 P53 P63 -- -- P73 -- P52 -- -- -- P72 -- P65DDR P64DDR P63DDR -- P81DDR P80DDR Port 8 P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9 P95 PA5 -- PB5 -- -- -- -- -- -- -- -- P94 PA4 -- PB4 -- -- -- -- -- -- -- -- P93 PA3 -- PB3 -- -- -- -- -- -- -- P92 PA2 -- PB2 -- -- -- -- -- -- -- P91 PA1 -- PB1 -- -- -- -- -- -- -- P90 PA0 -- PB0 -- -- -- -- -- -- -- Port B Port 9 Port A PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Port A PB7DDR -- PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Port B P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2 8 -- -- -- -- -- P53PCR P52PCR P51PCR P50PCR Port 5 Rev.3.00 Mar. 26, 2007 Page 595 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field Data Bus Width 8 8 8 8 8 8 8 8 8 8 Bit Names Bit 7 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE -- -- -- 8 8 8 8 8 8 8 8 8 8 8 AST7 -- WCE7 -- -- SSBY A23E -- -- -- -- IPRA7 IPRB7 -- -- -- -- -- Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- -- -- -- AST6 -- WCE6 -- -- STS2 A22E -- -- -- -- IPRA6 IPRB6 -- -- -- -- -- Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST -- -- -- -- AST5 -- WCE5 -- -- STS1 A21E Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- -- -- -- AST4 -- WCE4 -- -- STS0 -- Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- -- -- -- AST3 WMS1 WCE3 -- -- UE -- Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- -- -- -- AST2 WMS0 WCE2 -- MDS2 NMIEG -- -- -- -- -- IPRA2 IPRB2 -- -- -- -- -- Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- -- -- -- AST1 WC1 WCE1 -- MDS1 -- -- Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- -- -- -- AST0 WC0 WCE0 -- MDS0 RAME -- Bus controller System control Bus controller Module Name A/D Address Register (low) Name H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED H'EE H'EF H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF -- -- -- ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR -- -- -- ASTCR WCR WCER -- MDCR SYSCR ADRCR ISCR IER ISR -- IPRA IPRB -- -- IRQ5SC IRQ4SC -- IRQ5E IRQ5F -- -- -- -- -- -- -- -- IRQ4E IRQ4F -- IPRA4 -- -- -- -- -- -- -- -- -- IPRA3 IPRB3 -- -- -- -- -- IRQ1SC IRQ0SC Interrupt controller IRQ1E IRQ1F -- IPRA1 IPRB1 -- -- -- -- -- IRQ0E IRQ0F -- IPRA0 -- -- -- -- -- -- Legend: ITU: 16-bit integrated timer unit TPC: Programmable timing pattern controller WDT: Watchdog timer SCI: Serial communication interface A/D: A/D converter Notes: 1. The address depends on the output trigger setting. 2. For write access to TCSR, TCNT, and RSTCSR, see section 10.2.4, Notes on Register Access. Rev.3.00 Mar. 26, 2007 Page 596 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field B.2 Function Register name Address to which the register is mapped Name of on-chip supporting module Register acronym TSTR Timer Start Register H'60 ITU (all channels) Bit numbers Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 STR4 0 R/W 3 STR3 0 R/W 2 STR2 0 R/W 1 STR1 0 R/W 0 STR0 0 R/W Initial bit values Names of the bits. Dashes (--) indicate reserved bits. Possible types of access R W Read only Write only Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting Counter start 3 0 TCNT3 is halted 1 TCNT3 is counting Counter start 4 0 TCNT4 is halted 1 TCNT4 is counting R/W Read and write Full name of bit Descriptions of bit settings Rev.3.00 Mar. 26, 2007 Page 597 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field FLMCR--Flash Memory Control Register Bit 7 FWE Modes 1 to 4, and 6 Initial value Read/Write 0 R 1/0 R 6 SWE 0 R 0 R/W 5 ESU 0 R 0 R/W 4 PSU 0 R 0 R/W 3 EV 0 R 0 R/W 2 PV 0 R 0 R/W H'40 1 E 0 R 0 R/W 0 P 0 R 0 R/W Flash memory Modes Initial value 5 and 7 Read/Write Program mode 0 1 Program mode cleared (Initial value) Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase mode 0 1 Erase mode cleared (Initial value) Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, and ESU = 1 Program-verify mode 0 1 Program-verify mode cleared (Initial value) Transition to program-verify mode [Setting condition] When FWE = 1 and SWE = 1 Erase-verify mode 0 1 Erase-verify mode cleared (Initial value) Transition to erase-verify mode [Setting condition] When FWE = 1 and SWE = 1 Program setup 0 1 Program setup cleared (Initial value) Program setup [Setting condition] When FWE = 1 and SWE = 1 Erase setup 0 1 Erase setup cleared (Initial value) Erase setup [Setting condition] When FWE = 1 and SWE = 1 Software write enable bit 0 1 Program/erase disabled (Initial value) Program/erase enabled [Setting condition] When FWE = 1 Flash write enable bit 0 1 When a low level is input to the FWE pin (hardware protection state) When a high level is input to the FWE pin Note: This register is used only in the flash memory versions. Reading the corresponding address in a mask ROM version will always return 1s, and writes to this address are disabled. Fix the FWE pin low in mode 6. Rev.3.00 Mar. 26, 2007 Page 598 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field EBR--Erase Block Register Bit 7 EB7 Modes Initial value 1 to 4, and 6 Read/Write Modes Initial value 5 to 7 Read/Write 0 R 0 R/W 6 EB6 0 R 0 R/W 5 EB5 0 R 0 R/W 4 EB4 0 R 0 R/W H'42 3 EB3 0 R 0 R/W 2 EB2 0 R 0 R/W 1 Flash memory 0 EB0 0 R 0 R/W EB1 0 R 0 R/W Block 7 to 0 0 1 Block EB7 to EB0 is not selected (Initial value) Block EB7 to EB0 is selected Note: When not erasing flash memory, EBR should be cleared to H'00. This register is used only in the flash memory versions. Reading the corresponding address in a mask ROM version will always return 1s, and writes to this address are disabled. 1s cannot be set in this register in mode 6. Rev.3.00 Mar. 26, 2007 Page 599 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field RAMCR--RAM Control Register Bit 7 -- Modes Initial value 1 to 4 Read/Write Modes Initial value 5 to 7 Read/Write 1 -- 1 -- 6 -- 1 -- 1 -- 5 -- 1 -- 1 -- 4 -- 1 -- 1 -- H'47 3 RAMS 0 R 0 R/W* 2 RAM2 0 R 0 R/W* Flash Memory 1 RAM1 0 R 0 R/W* 0 -- 1 -- 1 -- Reserved bits RAM select, RAM2, RAM1 Bit 3 Bit 2 Bit 1 RAM Area H'FFF000 to H'FFF3FF H'000000 to H'0003FF H'000400 to H'0007FF H'000800 to H'000BFF H'000C00 to H'000FFF RAM Emulation Status No emulation Mapping RAM RAMS RAM2 RAM1 0 1 0/1 0 0/1 0 1 1 0 1 Note: This register is used only in the flash memory versions. Reading the corresponding address in a mask ROM version will always return 1s, and writes to this address are disabled. * In mode 6 (single-chip normal mode), flash memory emulation by RAM is not supported; these bits can be modified, but must not be set to 1. Rev.3.00 Mar. 26, 2007 Page 600 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field FLMSR--Flash Memory Status Register Bit 7 FLER Initial value Read/Write 0 R 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 H'4D 2 -- 1 -- 1 -- 1 -- Flash memory 0 -- 1 -- -- 1 -- Flash memory error 0 Flash memory write/erase protection is disabled (Initial value) 1 An error has occurred during flash memory writing/erasing Flash memory error protection is enabled DIVCR--Division Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 7 -- 1 -- H'5D 3 -- 1 -- 2 -- 1 -- 1 System control 0 DIV0 0 R/W DIV1 0 R/W Divide bits 1 and 0 Bit 1 Bit 0 Frequency DIV1 DIV0 Division Ratio 0 0 1/1initial value 1 1/2 1/4 0 1 1/8 1 Rev.3.00 Mar. 26, 2007 Page 601 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field MSTCR--Module Standby Control Register Bit Initial value Read/Write 7 PSTOP 0 R/W 6 -- 1 -- 5 0 R/W 4 0 R/W H'5E 3 0 R/W 2 -- 0 R/W 1 -- 0 System control 0 MSTOP0 0 R/W MSTOP5 MSTOP4 MSTOP3 R/W Module standby 0 0 A/D converter operates normally 1 A/D converter is in standby state Module standby 3 0 SCI1 operates normally 1 SCI1 is in standby state Module standby 4 0 SCI0 operates normally 1 SCI0 is in standby state Module standby 5 0 ITU operates normally 1 ITU is in standby state clock stop 0 clock output is enabled 1 clock output is disabled Rev.3.00 Mar. 26, 2007 Page 602 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TSTR--Timer Start Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 STR4 0 R/W H'60 3 STR3 0 R/W 2 STR2 0 R/W ITU (all channels) 1 STR1 0 R/W 0 STR0 0 R/W Counter start 0 0 TCNT0 is halted 1 TCNT0 is counting Counter start 1 0 TCNT1 is halted 1 TCNT1 is counting Counter start 2 0 TCNT2 is halted 1 TCNT2 is counting Counter start 3 0 TCNT3 is halted 1 TCNT3 is counting Counter start 4 0 TCNT4 is halted 1 TCNT4 is counting Rev.3.00 Mar. 26, 2007 Page 603 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TSNC--Timer Synchro Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 SYNC4 0 R/W H'61 3 SYNC3 0 R/W 2 SYNC2 0 R/W ITU (all channels) 1 SYNC1 0 R/W 0 SYNC0 0 R/W Timer sync 0 0 TCNT0 operates independently 1 TCNT0 is synchronized Timer sync 1 0 TCNT1 operates independently 1 TCNT1 is synchronized Timer sync 2 0 TCNT2 operates independently 1 TCNT2 is synchronized Timer sync 3 0 TCNT3 operates independently 1 TCNT3 is synchronized Timer sync 4 0 TCNT4 operates independently 1 TCNT4 is synchronized Rev.3.00 Mar. 26, 2007 Page 604 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TMDR--Timer Mode Register Bit Initial value Read/Write 7 -- 1 -- 6 MDF 0 R/W 5 FDIR 0 R/W 4 PWM4 0 R/W H'62 3 PWM3 0 R/W 2 PWM2 0 R/W ITU (all channels) 1 PWM1 0 R/W 0 PWM0 0 R/W PWM mode 0 0 Channel 0 operates normally 1 Channel 0 operates in PWM mode PWM mode 1 0 Channel 1 operates normally 1 Channel 1 operates in PWM mode PWM mode 2 0 Channel 2 operates normally 1 Channel 2 operates in PWM mode PWM mode 3 0 Channel 3 operates normally 1 Channel 3 operates in PWM mode PWM mode 4 0 Channel 4 operates normally 1 Channel 4 operates in PWM mode Flag direction 0 OVF is set to 1 in TSR2 when TCNT2 overflows or underflows 1 OVF is set to 1 in TSR2 when TCNT2 overflows Phase counting mode flag 0 Channel 2 operates normally 1 Channel 2 operates in phase counting mode Rev.3.00 Mar. 26, 2007 Page 605 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TFCR--Timer Function Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 CMD1 0 R/W 4 CMD0 0 R/W H'63 3 BFB4 0 R/W 2 BFA4 0 R/W ITU (all channels) 1 BFB3 0 R/W 0 BFA3 0 R/W Buffer mode A3 0 GRA3 operates normally 1 GRA3 is buffered by BRA3 Buffer mode B3 0 GRB3 operates normally 1 GRB3 is buffered by BRB3 Buffer mode A4 0 GRA4 operates normally 1 GRA4 is buffered by BRA4 Buffer mode B4 0 GRB4 operates normally 1 GRB4 is buffered by BRB4 Combination mode 1 and 0 Bit 5 Bit 4 Operating Mode of Channels 3 and 4 CMD1 CMD0 0 0 Channels 3 and 4 operate normally 1 0 1 Channels 3 and 4 operate together in complementary PWM mode 1 Channels 3 and 4 operate together in reset-synchronized PWM mode Rev.3.00 Mar. 26, 2007 Page 606 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TCR0--Timer Control Register 0 Bit Initial value Read/Write 7 -- 1 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W H'64 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 ITU0 CKEG1 CKEG0 TPSC0 0 R/W Timer prescaler 2 to 0 Bit 0 Bit 2 Bit 1 TPSC2 TPSC1 TPSC0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 TCNT Clock Source Internal clock: Internal clock: /2 Internal clock: /4 Internal clock: /8 External clock A: TCLKA input External clock B: TCLKB input External clock C: TCLKC input External clock D: TCLKD input Clock edge 1 and 0 Bit 4 Bit 3 Counted Edges of External Clock CKEG1 CKEG0 0 0 Rising edges counted 1 Falling edges counted 1 -- Both edges counted Counter clear 1 and 0 Bit 6 Bit 5 TCNT Clear Source CCLR1 CCLR0 0 0 TCNT is not cleared 1 TCNT is cleared by GRA compare match or input capture 1 0 TCNT is cleared by GRB compare match or input capture 1 Synchronous clear: TCNT is cleared in synchronization with other synchronized timers Rev.3.00 Mar. 26, 2007 Page 607 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TIOR0--Timer I/O Control Register 0 Bit Initial value Read/Write 7 -- 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'65 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 ITU0 IOA0 0 R/W I/O control A2 to A0 Bit 2 Bit 1 Bit 0 IOA2 IOA1 IOA0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 I/O control B2 to B0 Bit 6 Bit 5 Bit 4 IOB2 IOB1 IOB0 0 0 0 1 0 1 1 0 1 0 1 0 1 1 GRA Function GRA is an output compare register No output at compare match 0 output at GRA compare match 1 output at GRA compare match Output toggles at GRA compare match GRA captures rising edge of input GRA captures falling edge of input GRA captures both edges of input GRA is an input capture register GRB Function GRB is an output compare register No output at compare match 0 output at GRB compare match 1 output at GRB compare match Output toggles at GRB compare match GRB captures rising edge of input GRB captures falling edge of input GRB captures both edges of input GRB is an input capture register Rev.3.00 Mar. 26, 2007 Page 608 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TIER0--Timer Interrupt Enable Register 0 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'66 3 -- 1 -- 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 ITU0 IMIEA 0 R/W Input capture/compare match interrupt enable A 0 IMIA interrupt requested by IMFA is disabled 1 IMIA interrupt requested by IMFA is enabled Input capture/compare match interrupt enable B 0 IMIB interrupt requested by IMFB is disabled 1 IMIB interrupt requested by IMFB is enabled Overflow interrupt enable 0 OVI interrupt requested by OVF is disabled 1 OVI interrupt requested by OVF is enabled Rev.3.00 Mar. 26, 2007 Page 609 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TSR0--Timer Status Register 0 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'67 3 -- 1 -- 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* 0 ITU0 IMFA 0 R/(W)* Input capture/compare match flag A 0 [Clearing condition] Read IMFA when IMFA = 1, then write 0 in IMFA 1 [Setting conditions] * TCNT = GRA when GRA functions as a compare match register. * TCNT value is transferred to GRA by an input capture signal, when GRA functions as an input capture register. Input capture/compare match flag B 0 [Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 1 [Setting conditions] * TCNT = GRB when GRB functions as a compare match register. * TCNT value is transferred to GRB by an input capture signal, when GRB functions as an input capture register. Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 Note: * Only 0 can be written to clear the flag. Rev.3.00 Mar. 26, 2007 Page 610 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TCNT0 H/L--Timer Counter 0 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 H'68, H'69 6 0 5 0 4 0 3 0 2 0 1 0 ITU0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter GRA0 H/L--General Register A0 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'6A, H'6B 6 1 5 1 4 1 3 1 2 1 1 1 ITU0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register GRB0 H/L--General Register B0 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'6C, H'6D 6 1 5 1 4 1 3 1 2 1 1 1 ITU0 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register TCR1--Timer Control Register 1 Bit Initial value Read/Write 7 -- 1 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'6E 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 ITU1 TPSC0 0 R/W Note: Bit functions are the same as for ITU0. Rev.3.00 Mar. 26, 2007 Page 611 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TIOR1--Timer I/O Control Register 1 Bit Initial value Read/Write 7 -- 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'6F 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 ITU1 IOA0 0 R/W Note: Bit functions are the same as for ITU0. TIER1--Timer Interrupt Enable Register 1 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'70 3 -- 1 -- 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 ITU1 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. TSR1--Timer Status Register 1 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'71 3 -- 1 -- 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* 0 ITU1 IMFA 0 R/(W)* Notes: Bit functions are the same as for ITU0. * Only 0 can be written to clear the flag. TCNT1 H/L--Timer Counter 1 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 H'72, H'73 6 0 5 0 4 0 3 0 2 0 1 0 ITU1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. Rev.3.00 Mar. 26, 2007 Page 612 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field GRA1 H/L--General Register A1 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'74, H'75 6 1 5 1 4 1 3 1 2 1 1 1 ITU1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. GRB1 H/L--General Register B1 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'76, H'77 6 1 5 1 4 1 3 1 2 1 1 1 ITU1 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. TCR2--Timer Control Register 2 Bit Initial value Read/Write 7 -- 1 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'78 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 ITU2 TPSC0 0 R/W Notes: 1. Bit functions are the same as for ITU0. 2. When channel 2 is used in phase counting mode, the counter clock source selection by bits CKEG1, CKEG0 and TPSC2 to TPSC0 is ignored. Rev.3.00 Mar. 26, 2007 Page 613 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TIOR2--Timer I/O Control Register 2 Bit Initial value Read/Write 7 -- 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'79 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 ITU2 IOA0 0 R/W Notes: 1. Bit functions are the same as for ITU0. 2. Channel 2 does not have a compare match toggle output function. If this setting is used, 1 output will be selected automatically. TIER2--Timer Interrupt Enable Register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'7A 3 -- 1 -- 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 ITU2 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. Rev.3.00 Mar. 26, 2007 Page 614 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TSR2--Timer Status Register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'7B 3 -- 1 -- 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* 0 ITU2 IMFA 0 R/(W)* Overflow flag Bit functions are the same as for ITU0 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF Note: * Only 0 can be written to clear the flag. TCNT2 H/L--Timer Counter 2 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 H'7C, H'7D 6 0 5 0 4 0 3 0 2 0 1 0 ITU2 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Phase counting mode: up/down-counter Other modes: up-counter Rev.3.00 Mar. 26, 2007 Page 615 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field GRA2 H/L--General Register A2 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'7E, H'7F 6 1 5 1 4 1 3 1 2 1 1 1 ITU2 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. GRB2 H/L--General Register B2 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'80, H'81 6 1 5 1 4 1 3 1 2 1 1 1 ITU2 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU0. TCR3--Timer Control Register 3 Bit Initial value Read/Write 7 -- 1 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'82 3 CLEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 ITU3 TPSC0 0 R/W Note: Bit functions are the same as for ITU0. TIOR3--Timer I/O Control Register 3 Bit Initial value Read/Write 7 -- 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'83 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 ITU3 IOA0 0 R/W Note: Bit functions are the same as for ITU0. Rev.3.00 Mar. 26, 2007 Page 616 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TIER3--Timer Interrupt Enable Register 3 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'84 3 -- 1 -- 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 ITU3 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. TSR3--Timer Status Register 3 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'85 3 -- 1 -- 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* 0 ITU3 IMFA 0 R/(W)* Overflow flag Bit functions are the same as for ITU0 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT overflowed from H'FFFF to H'0000 or underflowed from H'0000 to H'FFFF Note: * Only 0 can be written to clear the flag. TCNT3 H/L--Timer Counter 3 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 H'86, H'87 6 0 5 0 4 0 3 0 2 0 1 0 ITU3 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Complementary PWM mode: up/down counter Other modes: up-counter Rev.3.00 Mar. 26, 2007 Page 617 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field GRA3 H/L--General Register A3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'88, H'89 6 1 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register (can be buffered) GRB3 H/L--General Register B3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'8A, H'8B 6 1 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Output compare or input capture register (can be buffered) BRA3 H/L--Buffer Register A3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'8C, H'8D 6 1 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Used to buffer GRA BRB3 H/L--Buffer Register B3 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'8E, H'8F 6 1 5 1 4 1 3 1 2 1 1 1 ITU3 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Used to buffer GRB Rev.3.00 Mar. 26, 2007 Page 618 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TOER--Timer Output Enable Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 EXB4 1 R/W 4 EXA4 1 R/W H'90 3 EB3 1 R/W 2 EB4 1 R/W ITU (all channels) 1 EA4 1 R/W 0 EA3 1 R/W Master enable TIOCA3 0 TIOCA 3 output is disabled regardless of TIOR3, TMDR, and TFCR settings 1 TIOCA 3 is enabled for output according to TIOR3, TMDR, and TFCR settings Master enable TIOCA4 0 TIOCA 4 output is disabled regardless of TIOR4, TMDR, and TFCR settings 1 TIOCA 4 is enabled for output according to TIOR4, TMDR, and TFCR settings Master enable TIOCB4 0 TIOCB4 output is disabled regardless of TIOR4 and TFCR settings 1 TIOCB4 is enabled for output according to TIOR4 and TFCR settings Master enable TIOCB3 0 TIOCB 3 output is disabled regardless of TIOR3 and TFCR settings 1 TIOCB 3 is enabled for output according to TIOR3 and TFCR settings Master enable TOCXA4 0 TOCXA 4 output is disabled regardless of TFCR settings 1 TOCXA 4 is enabled for output according to TFCR settings Master enable TOCXB4 0 TOCXB4 output is disabled regardless of TFCR settings 1 TOCXB4 is enabled for output according to TFCR settings Rev.3.00 Mar. 26, 2007 Page 619 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TOCR--Timer Output Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 XTGD 1 R/W H'91 3 -- 1 -- 2 -- 1 -- ITU (all channels) 1 OLS4 1 R/W 0 OLS3 1 R/W Output level select 3 0 TIOCB 3 , TOCXA 4, and TOCXB 4 outputs are inverted 1 TIOCB 3 , TOCXA 4, and TOCXB 4 outputs are not inverted Output level select 4 0 TIOCA 3 , TIOCA 4, and TIOCB 4 outputs are inverted 1 TIOCA 3 , TIOCA 4, and TIOCB 4 outputs are not inverted External trigger disable 0 Input capture A in channel 1 is used as an external trigger signal in reset-synchronized PWM mode and complementary PWM mode* 1 External triggering is disabled Note: * When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling ITU output. TCR4--Timer Control Register 4 Bit Initial value Read/Write 7 -- 1 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W H'92 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 ITU4 TPSC0 0 R/W Note: Bit functions are the same as for ITU0. Rev.3.00 Mar. 26, 2007 Page 620 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TIOR4--Timer I/O Control Register 4 Bit Initial value Read/Write 7 -- 1 -- 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W H'93 3 -- 1 -- 2 IOA2 0 R/W 1 IOA1 0 R/W 0 ITU4 IOA0 0 R/W Note: Bit functions are the same as for ITU0. TIER4--Timer Interrupt Enable Register 4 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'94 3 -- 1 -- 2 OVIE 0 R/W 1 IMIEB 0 R/W 0 ITU4 IMIEA 0 R/W Note: Bit functions are the same as for ITU0. TSR4--Timer Status Register 4 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'95 3 -- 1 -- 2 OVF 0 R/(W)* 1 IMFB 0 R/(W)* 0 ITU4 IMFA 0 R/(W)* Notes: Bit functions are the same as for ITU0. * Only 0 can be written to clear the flag. TCNT4 H/L--Timer Counter 4 H/L Bit Initial value Read/Write 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 H'96, H'97 6 0 5 0 4 0 3 0 2 0 1 0 ITU4 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. Rev.3.00 Mar. 26, 2007 Page 621 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field GRA4 H/L--General Register A4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'98, H'99 6 1 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. GRB4 H/L--General Register B4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'9A, H'9B 6 1 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. BRA4 H/L--Buffer Register A4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'9C, H'9D 6 1 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. BRB4 H/L--Buffer Register B4 H/L Bit Initial value Read/Write 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 H'9E, H'9F 6 1 5 1 4 1 3 1 2 1 1 1 ITU4 0 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: Bit functions are the same as for ITU3. Rev.3.00 Mar. 26, 2007 Page 622 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TPMR--TPC Output Mode Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'A0 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W TPC G3NOV G2NOV G1NOV G0NOV Group 0 non-overlap 0 Normal TPC output in group 0 Output values change at compare match A in the selected ITU channel 1 Non-overlapping TPC output in group 0, controlled by compare match A and B in the selected ITU channel Group 1 non-overlap 0 Normal TPC output in group 1 Output values change at compare match A in the selected ITU channel 1 Non-overlapping TPC output in group 1, controlled by compare match A and B in the selected ITU channel Group 2 non-overlap 0 Normal TPC output in group 2 Output values change at compare match A in the selected ITU channel 1 Non-overlapping TPC output in group 2, controlled by compare match A and B in the selected ITU channel Group 3 non-overlap 0 Normal TPC output in group 3 Output values change at compare match A in the selected ITU channel 1 Non-overlapping TPC output in group 3, controlled by compare match A and B in the selected ITU channel Rev.3.00 Mar. 26, 2007 Page 623 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TPCR--TPC Output Control Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'A1 3 1 R/W 2 1 R/W 1 1 R/W 0 1 TPC G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 R/W Group 0 compare match select 1 and 0 Bit 1 0 1 Bit 0 0 1 0 1 G0CMS1 G0CMS0 ITU Channel Selected as Output Trigger TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 0 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 1 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 2 TPC output group 0 (TP3 to TP0) is triggered by compare match in ITU channel 3 Group 1 compare match select 1 and 0 Bit 3 0 1 Bit 2 ITU Channel Selected as Output Trigger TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 0 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 1 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 2 TPC output group 1 (TP7 to TP4) is triggered by compare match in ITU channel 3 0 1 0 1 G1CMS1 G1CMS0 Group 2 compare match select 1 and 0 Bit 5 0 1 Bit 4 0 1 0 1 ITU Channel Selected as Output Trigger TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 0 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 1 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 2 TPC output group 2 (TP11 to TP8) is triggered by compare match in ITU channel 3 G2CMS1 G2CMS0 Group 3 compare match select 1 and 0 Bit 7 0 1 Bit 6 0 1 0 1 G3CMS1 G3CMS0 ITU Channel Selected as Output Trigger TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 0 TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 1 TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 2 TPC output group 3 (TP15 to TP12)* is triggered by compare match in ITU channel 3 Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip. Rev.3.00 Mar. 26, 2007 Page 624 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field NDERB--Next Data Enable Register B Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'A2 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W TPC NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Next data enable 15 to 8 Bits 7 to 0 Description NDER15 to NDER8 0 TPC outputs TP15 to TP 8* are disabled (NDR15 to NDR8 are not transferred to PB 7 to PB 0 ) 1 TPC outputs TP15 to TP 8* are enabled (NDR15 to NDR8 are transferred to PB 7 to PB 0 ) Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip. NDERA--Next Data Enable Register A Bit Initial value Read/Write 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 0 R/W H'A3 3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0 R/W TPC NDER4 NDER3 NDER1 NDER0 Next data enable 7 to 0 Bits 7 to 0 Description NDER7 to NDER0 0 TPC outputs TP 7 to TP 0 are disabled (NDR7 to NDR0 are not transferred to PA 7 to PA 0) TPC outputs TP 7 to TP 0 are enabled 1 (NDR7 to NDR0 are transferred to PA 7 to PA 0) Rev.3.00 Mar. 26, 2007 Page 625 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field NDRB--Next Data Register B * Same output trigger for TPC output groups 2 and 3 Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W H'A4/H'A6 TPC 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Next output data for TPC output group 3* Next output data for TPC output group 2 Address H'FFA6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- * Different output triggers for TPC output groups 2 and 3 Address H'FFA4 Bit Initial value Read/Write 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Next output data for TPC output group 3* Address H'FFA6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Next output data for TPC output group 2 Note: * Since this LSI does not have a TP14 pin, the TP14 signal cannot be output off-chip. Rev.3.00 Mar. 26, 2007 Page 626 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field NDRA--Next Data Register A * Same output trigger for TPC output groups 0 and 1 Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W H'A5/H'A7 TPC 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next output data for TPC output group 1 Next output data for TPC output group 0 Address H'FFA7 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- * Different output triggers for TPC output groups 0 and 1 Address H'FFA5 Bit Initial value Read/Write 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Next output data for TPC output group 1 Address H'FFA7 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Next output data for TPC output group 0 Rev.3.00 Mar. 26, 2007 Page 627 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TCSR--Timer Control/Status Register Bit Initial value Read/Write 7 OVF 0 R/(W)* 6 WT/ IT 0 R/W 5 TME 0 R/W 4 -- 1 -- H'A8 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 WDT CKS0 0 R/W Clock select 2 to 0 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Timer enable 0 TCNT is initialized to H'00 and halted 1 TCNT is counting Timer mode select 0 Interval timer: requests interval timer interrupts 1 Watchdog timer: generates a reset signal Overflow flag 0 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 1 [Setting condition] TCNT changes from H'FF to H'00 Description /2 /32 /64 /128 /256 /512 /2048 /4096 Note: * Only 0 can be written to clear the flag. Rev.3.00 Mar. 26, 2007 Page 628 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TCNT--Timer Counter H'A9 (read), H'A8 (write) 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT Bit Initial value Read/Write 7 0 R/W R/W Count value RSTCSR--Reset Control/Status Register H'AB (read), H'AA (write) 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- WDT Bit Initial value Read/Write 7 WRST 0 R/(W)* 6 RSTOE 0 R/W 5 -- 1 -- Reset output enable 0 Reset signal is not output externally 1 Reset signal is output externally Watchdog timer reset 0 [Clearing condition] Reset signal input at RES pin, or 0 written by software 1 [Setting condition] TCNT overflow generates a reset signal Note: * Only 0 can be written in bit 7 to clear the flag. Rev.3.00 Mar. 26, 2007 Page 629 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field SMR--Serial Mode Register Bit Initial value Read/Write 7 C/ A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 7 O/ E 0 R/W H'B0 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI0 CKS0 0 R/W Clock select 1 and 0 Bit 1 Bit 0 Clock Source CKS1 CKS0 0 0 clock 1 /4 clock /16 clock 0 1 /64 clock 1 Multiprocessor mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop bit length 0 One stop bit 1 Two stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit is not added or checked 1 Parity bit is added and checked Character length 0 8-bit data 1 7-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode Rev.3.00 Mar. 26, 2007 Page 630 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field BRR--Bit Rate Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'B1 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 R/W Serial communication bit rate setting Rev.3.00 Mar. 26, 2007 Page 631 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field SCR--Serial Control Register Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'B2 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI0 CKE0 0 R/W Clock enable 1 and 0 Bit 1 Bit 2 Clock Selection and Output CKE1 CKE2 0 Asynchronous mode Internal clock, SCK pin available for generic input/output 0 Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode Internal clock, SCK pin used for clock output 1 Synchronous mode Internal clock, SCK pin used for serial clock output Asynchronous mode External clock, SCK pin used for clock input 0 1 Synchronous mode External clock, SCK pin used for serial clock input Asynchronous mode External clock, SCK pin used for clock input 1 Synchronous mode External clock, SCK pin used for serial clock input Transmit-end interrupt enable 0 Transmit-end interrupt requests (TEI) are disabled 1 Transmit-end interrupt requests (TEI) are enabled Multiprocessor interrupt enable 0 Multiprocessor interrupts are disabled (normal receive operation) 1 Multiprocessor interrupts are enabled Transmit enable 0 Transmitting is disabled 1 Transmitting is enabled Receive enable 0 Receiving is disabled 1 Receiving is enabled Receive interrupt enable 0 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are disabled 1 Receive-data-full (RXI) and receive-error (ERI) interrupt requests are enabled Transmit interrupt enable 0 Transmit-data-empty interrupt request (TXI) is disabled 1 Transmit-data-empty interrupt request (TXI) is enabled Rev.3.00 Mar. 26, 2007 Page 632 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field TDR--Transmit Data Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'B3 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI0 R/W Serial transmit data Rev.3.00 Mar. 26, 2007 Page 633 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field SSR--Serial Status Register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* H'B4 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 SCI0 MPBT 0 R/W Multiprocessor bit 0 Multiprocessor bit value in receive data is 0 1 Transmit end 0 1 Multiprocessor bit value in receive data is 1 Multiprocessor bit transfer 0 Multiprocessor bit value in transmit data is 0 1 Multiprocessor bit value in transmit data is 1 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. [Setting conditions] Reset or transition to standby mode. TE is cleared to 0 in SCR. TDRE is 1 when last bit of serial character is transmitted. Parity error 0 [Clearing conditions] Reset or transition to standby mode. Read PER when PER = 1, then write 0 in PER. [Setting condition] Parity error: (parity of receive data does not match parity setting of O/ E in SMR) [Clearing conditions] Reset or transition to standby mode. Read ORER when ORER = 1, then write 0 in ORER. [Setting condition] Overrun error (reception of next serial data ends when RDRF = 1) Framing error 0 [Clearing conditions] Reset or transition to standby mode. Read FER when FER = 1, then write 0 in FER. [Setting condition] Framing error (stop bit is 0) 1 1 Overrun error Receive data register full 0 [Clearing conditions] Reset or transition to standby mode. Read RDRF when RDRF = 1, then write 0 in RDRF. [Setting condition] Serial data is received normally and transferred from RSR to RDR 0 1 1 Transmit data register empty 0 1 [Clearing conditions] Read TDRE when TDRE = 1, then write 0 in TDRE. [Setting conditions] Reset or transition to standby mode. TE is 0 in SCR Data is transferred from TDR to TSR, enabling new data to be written in TDR. Note: * Only 0 can be written to clear the flag. Rev.3.00 Mar. 26, 2007 Page 634 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field RDR--Receive Data Register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'B5 3 0 R 2 0 R 1 0 R 0 0 R SCI0 Serial receive data SCMR--Smart Card Mode Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'B6 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SCI0 SMIF 0 R/W Smart card interface mode select 0 Smart card interface function is disabled 1 Smart card interface function is enabled Smart card data invert 0 Unmodified TDR contents are transmitted Received data is stored unmodified in RDR 1 Inverted 1/0 logic levels of TDR contents are transmitted 1/0 logic levels of received data are inverted before storage in RDR Smart card data transfer direction 0 TDR contents are transmitted LSB-first Received data is stored LSB-first in RDR 1 TDR contents are transmitted MSB-first Received data is stored MSB-first in RDR Rev.3.00 Mar. 26, 2007 Page 635 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field SMR--Serial Mode Register Bit Initial value Read/Write 7 C/ A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 7 O/ E 0 R/W H'B8 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI1 CKS0 0 R/W Note: Bit functions are the same as for SCI0. BRR--Bit Rate Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'B9 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI1 R/W Note: Bit functions are the same as for SCI0. SCR--Serial Control Register Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W H'BA 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI1 CKE0 0 R/W Note: Bit functions are the same as for SCI0. TDR--Transmit Data Register Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'BB 3 1 R/W 2 1 R/W 1 1 R/W 0 1 SCI1 R/W Note: Bit functions are the same as for SCI0. Rev.3.00 Mar. 26, 2007 Page 636 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field SSR--Serial Status Register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* H'BC 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 SCI1 MPBT 0 R/W Notes: Bit functions are the same as for SCI0. * Only 0 can be written to clear the flag. RDR--Receive Data Register Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'BD 3 0 R 2 0 R 1 0 R 0 0 R SCI1 Note: Bit functions are the same as for SCI0. P1DDR--Port 1 Data Direction Register Bit Modes Initial value 1 and 3 Read/Write Modes 5 to 7 Initial value Read/Write 7 1 -- 0 W 6 1 -- 0 W 5 1 -- 0 W 4 1 -- 0 W H'C0 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W Port 1 0 1 -- 0 W P17 DDR P16 DDR P15 DDR P14 DDR P13 DDR P12 DDR P11 DDR P10 DDR Port 1 input/output select 0 Generic input pin 1 Generic output pin Rev.3.00 Mar. 26, 2007 Page 637 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field P2DDR--Port 2 Data Direction Register Bit Modes Initial value 1 and 3 Read/Write Modes Initial value 5 to 7 Read/Write 7 1 -- 0 W 6 1 -- 0 W 5 1 -- 0 W 4 1 -- 0 W H'C1 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W Port 2 0 1 -- 0 W P27 DDR P26 DDR P25 DDR P24 DDR P23 DDR P22 DDR P21 DDR P20 DDR Port 2 input/output select 0 Generic input pin 1 Generic output pin P1DR--Port 1 Data Register Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W H'C2 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 Port 1 P10 0 R/W Data for port 1 pins P2DR--Port 2 Data Register Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W H'C3 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 Port 2 P20 0 R/W Data for port 2 pins Rev.3.00 Mar. 26, 2007 Page 638 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field P3DDR--Port 3 Data Direction Register Bit Initial value Read/Write 7 0 W 6 0 W 5 0 W 4 0 W H'C4 3 0 W 2 0 W 1 0 W 0 0 Port 3 P3 7 DDR P3 6 DDR P3 5 DDR P3 4 DDR P3 3 DDR P3 2 DDR P3 1 DDR P3 0 DDR W Port 3 input/output select 0 Generic input pin 1 Generic output pin P3DR--Port 3 Data Register Bit Initial value Read/Write 7 P3 7 0 R/W 6 P3 6 0 R/W 5 P3 5 0 R/W 4 P3 4 0 R/W H'C6 3 P3 3 0 R/W 2 P3 2 0 R/W 1 P3 1 0 R/W 0 Port 3 P3 0 0 R/W Data for port 3 pins P5DDR--Port 5 Data Direction Register Bit Modes Initial value 1 and 3 Read/Write Modes 5 to 7 Initial value Read/Write 7 -- 1 -- 1 -- 6 -- 1 -- 1 -- 5 -- 1 -- 1 -- 4 -- 1 -- 1 -- H'C8 3 1 -- 0 W 2 1 -- 0 W 1 1 -- 0 W Port 5 0 1 -- 0 W P5 3 DDR P5 2 DDR P5 1 DDR P5 0 DDR Port 5 input/output select 0 Generic input 1 Generic output Rev.3.00 Mar. 26, 2007 Page 639 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field P6DDR--Port 6 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 0 W 5 0 W 4 0 W H'C9 3 0 W 2 -- 0 W 1 -- 0 W 0 Port 6 P6 5 DDR P6 4 DDR P6 3 DDR P6 0 DDR 0 W Port 6 input/output select 0 Generic input 1 Generic output P5DR--Port 5 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'CA 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 Port 5 P50 0 R/W Data for port 5 pins P6DR--Port 6 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 0 R/W 5 P6 5 0 R/W 4 P6 4 0 R/W H'CB 3 P6 3 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 Port 6 P6 0 0 R/W Data for port 6 pins Rev.3.00 Mar. 26, 2007 Page 640 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field P8DDR--Port 8 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 W H'CD 3 -- 0 W 2 -- 0 W 1 0 W 0 0 Port 8 P8 1 DDR P8 0 DDR W Port 8 input/output select 0 Generic input 1 Generic output P7DR--Port 7 Data Register Bit Initial value Read/Write 7 P77 --* R 6 P76 --* R 5 P75 --* R 4 P74 --* R H'CE 3 P73 --* R 2 P72 --* R 1 P71 --* R 0 Port 7 P70 --* R Data for port 7 pins Note: * Determined by pins P77 to P70. P8DR--Port 8 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 0 R/W H'CF 3 -- 0 R/W 2 -- 0 R/W 1 P8 1 0 R/W 0 Port 8 P8 0 0 R/W Data for port 8 pins Rev.3.00 Mar. 26, 2007 Page 641 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field P9DDR--Port 9 Data Direction Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 0 W 4 0 W H'D0 3 0 W 2 0 W 1 0 W 0 0 Port 9 P95DDR P9 4 DDR P93DDR P9 2 DDR P91DDR P9 0 DDR W Port 9 input/output select 0 Generic input 1 Generic output PADDR--Port A Data Direction Register Bit Initial value Read/Write Modes 1 and 5 to 7 Initial value Read/Write 7 1 -- 0 W 6 0 W 0 W 5 0 W 0 W 4 0 W 0 W H'D1 3 0 W 0 W 2 0 W 0 W 1 0 W 0 W Port A 0 0 W 0 W PA 7 DDR PA 6 DDR PA 5 DDR PA 4 DDR PA 3 DDR PA 2 DDR PA 1 DDR PA 0 DDR Mode 3 Port A input/output select 0 Generic input 1 Generic output P9DR--Port 9 Data Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 P95 0 R/W 4 P94 0 R/W H'D2 3 P93 0 R/W 2 P92 0 R/W 1 P91 0 R/W 0 Port 9 P90 0 R/W Data for port 9 pins Rev.3.00 Mar. 26, 2007 Page 642 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field PADR--Port A Data Register Bit Initial value Read/Write 7 PA 7 0 R/W 6 PA 6 0 R/W 5 PA 5 0 R/W 4 PA 4 0 R/W H'D3 3 PA 3 0 R/W 2 PA 2 0 R/W 1 PA 1 0 R/W Port A 0 PA 0 0 R/W Data for port A pins PBDDR--Port B Data Direction Register Bit Initial value Read/Write 7 PB7 DDR 0 W 6 -- 0 W 5 0 W 4 0 W H'D4 3 0 W 2 0 W 1 0 W Port B 0 0 W PB5 DDR PB4 DDR PB3 DDR PB2 DDR PB1 DDR PB0 DDR Port B input/output select 0 Generic input 1 Generic output PBDR--Port B Data Register Bit Initial value Read/Write 7 PB 7 0 R/W 6 -- 0 R/W 5 PB 5 0 R/W 4 PB 4 0 R/W H'D6 3 PB 3 0 R/W 2 PB 2 0 R/W 1 PB 1 0 R/W Port B 0 PB 0 0 R/W Data for port B pins Rev.3.00 Mar. 26, 2007 Page 643 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field P2PCR--Port 2 Input Pull-Up Control Register Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'D8 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port 2 P2 7 PCR P2 6 PCR P2 5 PCR P2 4 PCR P2 3 PCR P2 2 PCR P2 1 PCR P2 0 PCR R/W Port 2 input pull-up control 7 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P2DDR bit is cleared to 0 (designating generic input). P5PCR--Port 5 Input Pull-Up Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'DB 3 0 R/W 2 0 R/W 1 0 R/W 0 0 Port 5 P5 3 PCR P5 2 PCR P5 1 PCR P5 0 PCR R/W Port 5 input pull-up control 3 to 0 0 Input pull-up transistor is off 1 Input pull-up transistor is on Note: Valid when the corresponding P5DDR bit is cleared to 0 (designating generic input). ADDRA H/L--A/D Data Register A H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'E0, H'E1 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R A/D 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- ADDRAH A/D conversion data 10-bit data giving an A/D conversion result ADDRAL Rev.3.00 Mar. 26, 2007 Page 644 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field ADDRB H/L--A/D Data Register B H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'E2, H'E3 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R A/D 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- ADDRBH A/D conversion data 10-bit data giving an A/D conversion result ADDRBL ADDRC H/L--A/D Data Register C H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'E4, H'E5 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R A/D 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- ADDRCH A/D conversion data 10-bit data giving an A/D conversion result ADDRCL ADDRD H/L--A/D Data Register D H/L Bit Initial value Read/Write 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R H'E6, H'E7 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R A/D 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- ADDRDH A/D conversion data 10-bit data giving an A/D conversion result ADDRDL Rev.3.00 Mar. 26, 2007 Page 645 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field ADCR--A/D Control Register Bit Initial value Read/Write 7 TRGE 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'E9 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- A/D Trigger enable 0 A/D conversion cannot be externally triggered 1 A/D conversion starts at the fall of the external trigger signal ( ADTRG ) Rev.3.00 Mar. 26, 2007 Page 646 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field ADCSR--A/D Control/Status Register Bit Initial value Read/Write 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'E8 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W A/D Clock select 0 Conversion time = 266 states (maximum) 1 Conversion time = 134 states (maximum) Channel select 2 to 0 Group Channel Selection Selection CH2 CH1 CH0 0 0 0 1 0 1 1 0 0 1 1 0 1 1 Description Single Mode AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Scan Mode AN 0 AN 0, AN 1 AN 0 to AN 2 AN 0 to AN 3 AN 4 AN 4, AN 5 AN 4 to AN 6 AN 4 to AN 7 Scan mode 0 Single mode 1 Scan mode A/D start 0 A/D conversion is stopped 1 Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software, by a reset, or by a transition to standby mode A/D interrupt enable 0 A/D end interrupt request is disabled 1 A/D end interrupt request is enabled A/D end flag 0 [Clearing condition] Read ADF while ADF = 1, then write 0 in ADF 1 [Setting conditions] Single mode: A/D conversion ends Scan mode: A/D conversion ends in all selected channels Note: * Only 0 can be written to clear flag. Rev.3.00 Mar. 26, 2007 Page 647 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field ASTCR--Access State Control Register Bit Initial value Read/Write 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'ED 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 access state control Bits 7 to 0 Number of States in Access Cycle AST7 to AST0 0 Areas 7 to 0 are two-state access areas Areas 7 to 0 are three-state access areas 1 WCR--Wait Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- H'EE 3 WMS1 0 R/W 2 WMS0 0 R/W 1 Bus controller 0 WC0 1 R/W WC1 1 R/W Wait mode select 1 and 0 Bit 3 Bit 2 Wait Mode WMS1 WMS0 0 0 Programmable wait mode 1 No wait states inserted by wait-state controller 1 0 1 Pin wait mode 1 Pin auto-wait mode Wait count 1 and 0 Bit 1 Bit 0 Number of Wait States WC1 WC0 0 0 No wait states inserted by wait-state controller 1 1 0 1 1 state inserted 2 states inserted 3 states inserted Rev.3.00 Mar. 26, 2007 Page 648 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field WCER--Wait Controller Enable Register Bit Initial value Read/Write 7 WCE7 1 R/W 6 WCE6 1 R/W 5 WCE5 1 R/W 4 WCE4 1 R/W H'EF 3 WCE3 1 R/W 2 WCE2 1 R/W 1 Bus controller 0 WCE0 1 R/W WCE1 1 R/W Wait state controller enable 7 to 0 0 Wait-state control is disabled (pin wait mode 0) 1 Wait-state control is enabled MDCR--Mode Control Register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'F1 3 -- 0 -- 2 MDS2 --* R 1 System control 0 MDS0 --* R MDS1 --* R Mode select 2 to 0 Bit 1 Bit 0 Bit 2 MD1 MD0 MD2 0 0 1 0 0 1 1 0 0 1 1 1 0 1 Note: * Determined by the state of the mode pins (MD2 to MD0). Operating mode -- Mode 1 -- Mode 3 -- Mode 5 Mode 6 Mode 7 Rev.3.00 Mar. 26, 2007 Page 649 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field SYSCR--System Control Register Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'F2 3 UE 1 R/W 2 NMIEG 0 R/W 1 -- 1 -- System control 0 RAME 1 R/W RAM enable 0 On-chip RAM is disabled 1 On-chip RAM is enabled NMI edge select 0 An interrupt is requested at the falling edge of NMI 1 An interrupt is requested at the rising edge of NMI User bit enable 0 CCR bit 6 (UI) is used as an interrupt mask bit 1 CCR bit 6 (UI) is used as a user bit Standby timer select 2 to 0 Bit 6 Bit 5 Bit 4 Standby Timer STS2 STS1 STS0 0 0 0 Waiting time = 8192 states 1 Waiting time = 16384 states 0 Waiting time = 32768 states 1 1 Waiting time = 65536 states Waiting time = 131072 states 1 0 -- Illegal setting -- 1 Software standby 0 SLEEP instruction causes transition to sleep mode 1 SLEEP instruction causes transition to software standby mode Rev.3.00 Mar. 26, 2007 Page 650 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field ADRCR--Address Control Register H'F3 Bus controller Bit Modes 1 and 5 to 7 Mode 3 Initial value Read/Write Initial value Read/Write 7 A23E 1 -- 1 R/W 6 A22E 1 -- 1 R/W 5 A21E 1 -- 1 R/W 4 -- 1 -- 1 -- 3 -- 1 -- 1 -- 2 -- 1 -- 1 -- 1 -- 1 -- 1 -- 0 -- 0 R/W 0 R/W Address 23 to 21 enable 0 Address output 1 I/O pins other than the above Rev.3.00 Mar. 26, 2007 Page 651 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field ISCR--IRQ Sense Control Register Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 0 R/W 4 0 R/W H'F4 3 -- 0 R/W 2 -- 0 R/W Interrupt controller 1 0 R/W 0 0 R/W IRQ5SC IRQ4SC IRQ1SC IRQ0SC IRQ5, IRQ4, IRQ1 and IRQ0 sense control 0 Interrupts are requested when IRQ5, IRQ4, IRQ1, and IRQ0 inputs are low 1 Interrupts are requested by falling-edge input at IRQ5, IRQ4, IRQ1 and IRQ0 IER--IRQ Enable Register Bit Initial value Read/Write 7 -- 0 R/W 6 -- 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W H'F5 3 -- 0 R/W 2 -- 0 R/W Interrupt controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ5, IRQ4, IRQ1, IRQ0 enable 0 IRQ5, IRQ4, IRQ1 and IRQ0 interrupts are disabled 1 IRQ5, IRQ4, IRQ1 and IRQ0 interrupts are enabled Rev.3.00 Mar. 26, 2007 Page 652 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field ISR--IRQ Status Register Bit Initial value Read/Write 7 -- 0 -- 6 -- 0 -- 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* H'F6 3 -- 0 -- 2 -- 0 -- Interrupt controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ5, IRQ4, IRQ1 and IRQ0 flags Bits 5, 4, 1 and 0 IRQ5F IRQ4F IRQ1F IRQ0F 0 Setting and Clearing Conditions [Clearing conditions] * Read IRQnF when IRQnF = 1, then write 0 in IRQnF. * IRQnSC = 0, IRQn input is high, and interrupt exception handling is carried out. * IRQnSC = 1 and IRQn interrupt exception handling is carried out. [Setting conditions] * IRQnSC = 0 and IRQn input is low. * IRQnSC = 1 and IRQn input changes from high to low. 1 Note: n = 5, 4, 1 and 0 Note: * Only 0 can be written to clear the flag. Rev.3.00 Mar. 26, 2007 Page 653 of 682 REJ09B0353-0300 Appendix B Internal I/O Register Field IPRA--Interrupt Priority Register A Bit Initial value Read/Write 7 IPRA7 0 R/W 6 IPRA6 0 R/W 5 -- 0 R/W 4 IPRA4 0 R/W H'F8 3 IPRA3 0 R/W 2 IPRA2 0 R/W Interrupt controller 1 IPRA1 0 R/W 0 IPRA0 0 R/W Priority level A7, A6, A4 to A0 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) * Interrupt sources controlled by each bit Bit 7 IPRA7 Interrupt source IRQ0 Bit 6 IPRA6 IRQ1 Bit 5 -- -- Bit 4 IPRA4 IRQ4, IRQ5 Bit 3 IPRA3 WDT Bit 2 IPRA2 ITU channel 0 Bit 1 IPRA1 ITU channel 1 Bit 0 IPRA0 ITU channel 2 IPRB--Interrupt Priority Register B Bit Initial value Read/Write 7 IPRB7 0 R/W 6 IPRB6 0 R/W 5 -- 0 R/W 4 -- 0 R/W H'F9 3 IPRB3 0 R/W 2 IPRB2 0 R/W Interrupt controller 1 IPRB1 0 R/W 0 -- 0 R/W Priority level B7, B6, B3 to B1 0 Priority level 0 (low priority) 1 Priority level 1 (high priority) * Interrupt sources controlled by each bit Bit 7 IPRB7 Interrupt source ITU channel 3 Bit 6 IPRB6 ITU channel 4 Bit 5 -- -- Bit 4 -- -- Bit 3 IPRB3 SCI channel 0 Bit 2 IPRB2 SCI channel 1 Bit 1 IPRB1 Bit 0 -- A/D -- converter Rev.3.00 Mar. 26, 2007 Page 654 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Appendix C I/O Block Diagrams C.1 Port 1 Block Diagram Software standby Modes 6 and 7 Internal data bus (upper) Hardware standby Modes 1, 3, and 5 Reset S R Q D P1nDDR C WP1D Modes 6 and 7 Reset R P1n Q P1nDR C Modes 1, 3, and 5 WP1 D * RP1 Legend: WP1D: Write to P1DDR WP1: Write to port 1 RP1: Read port 1 Notes: n = 0 to 7 * Set priority Figure C.1 Port 1 Block Diagram Rev.3.00 Mar. 26, 2007 Page 655 of 682 REJ09B0353-0300 Internal address bus Appendix C I/O Block Diagrams C.2 Port 2 Block Diagram Reset Q Modes Software standby 6 and 7 Hardware standby RP2P Modes 1, 3, and 5 S D P2nPCR C WP2P Reset R Internal data bus (upper) * R Q D P2nDDR C Modes 6 and 7 WP2D Reset R P2n Q P2nDR C Modes 1, 3, and 5 WP2 D RP2 Legend: WP2P: Write to P2PCR RP2P: Read P2PCR WP2D: Write to P2DDR WP2: Write to port 2 RP2: Read port 2 Notes: n = 0 to 7 * Set priority Figure C.2 Port 2 Block Diagram Rev.3.00 Mar. 26, 2007 Page 656 of 682 REJ09B0353-0300 Internal address bus Appendix C I/O Block Diagrams C.3 Port 3 Block Diagram Internal data bus (upper) Reset Hardware standby Modes 6 and 7 Write to external address R Q D P3nDDR C WP3D Reset Modes 6 and 7 P3n Q R P3nDR C Modes 1, 3, and 5 WP3 D RP3 Read external address Legend: WP3D: Write to P3DDR WP3: Write to port 3 RP3: Read port 3 Note: n = 0 to 7 Figure C.3 Port 3 Block Diagram Rev.3.00 Mar. 26, 2007 Page 657 of 682 REJ09B0353-0300 Internal data bus (lower) Appendix C I/O Block Diagrams C.4 Port 5 Block Diagram Reset Q Software standby Hardware standby Modes 6 and 7 RP5P D P5nPCR C WP5P Modes 1, 3 Reset S R Q D P5nDDR C Modes 6 and 7 WP5D Reset R P5n Q P5nDR C Modes 1, 3, and 5 WP5 D * Internal data bus (upper) R RP5 Legend: WP5P: Write to P5PCR RP5P: Read P5PCR WP5D: Write to P5DDR WP5: Write to port 5 RP5: Read port 5 Notes: n = 0 to 3 * Set priority Figure C.4 Port 5 Block Diagram Rev.3.00 Mar. 26, 2007 Page 658 of 682 REJ09B0353-0300 Internal address bus Appendix C I/O Block Diagrams C.5 Port 6 Block Diagram Reset R Q D P60DDR Modes 6 and 7 C WP6D Reset R P60 Q P60DR C WP6 D Internal data bus Bus controller WAIT input enable RP6 Bus controller WAIT output Legend: WP6D: Write to P6DDR WP6: Write to port 6 RP6: Read port 6 Figure C.5 (a) Port 6 Block Diagram (Pin P60) Rev.3.00 Mar. 26, 2007 Page 659 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Software standby Modes 6 and 7 Hardware standby Reset Q D P6nDDR C WP6D Reset Modes 6 and 7 P6n Q R P6nDR C WP6 AS output RD output WR output D Modes 1, 3, and 5 RP6 Legend: WP6D: Write to P6DDR Write to port 6 WP6: Read port 6 RP6: Note: n = 3 to 5 Figure C.5 (b) Port 6 Block Diagram (Pins P63 to P65) Rev.3.00 Mar. 26, 2007 Page 660 of 682 REJ09B0353-0300 Internal data bus R Appendix C I/O Block Diagrams C.6 Port 7 Block Diagram Internal data bus A/D converter Input enable Analog input RP7 P7n Legend: RP7: Read port 7 Note: n = 0 to 7 Figure C.6 Port 7 Block Diagram Rev.3.00 Mar. 26, 2007 Page 661 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams C.7 Port 8 Block Diagram Reset Q D P80DDR C WP8D Reset R P80 Q P80DR C WP8 D RP8 Internal data bus Interrupt controller IRQ0 input R Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.7(a) Port 8 Block Diagram (Pin P80) Rev.3.00 Mar. 26, 2007 Page 662 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Reset Q D P81DDR C WP8D Reset Modes 6 and 7 P81 Modes 1, 3, and 5 R Q P81DR C WP8 D RP8 Internal data bus Interrupt controller IRQ1 input R Legend: WP8D: Write to P8DDR WP8: Write to port 8 RP8: Read port 8 Figure C.7 (b) Port 8 Block Diagram (Pin P81) Rev.3.00 Mar. 26, 2007 Page 663 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams C.8 Port 9 Block Diagram Reset R Q D P90DDR C WP9D Reset R Q D SCI0 Output enable Serial transmit data Guard time Internal data bus P90 P90DR C WP9 RP9 Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.8 (a) Port 9 Block Diagram (Pin P90) Rev.3.00 Mar. 26, 2007 Page 664 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Reset R Q D P91DDR C WP9D Reset R P91 Q P91DR C WP9 Output enable Serial transmit data D SCI1 RP9 Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Figure C.8 (b) Port 9 Block Diagram (Pin P91) Rev.3.00 Mar. 26, 2007 Page 665 of 682 REJ09B0353-0300 Internal data bus Appendix C I/O Block Diagrams R Q D P9nDDR C WP9D Reset R P9n Q P9nDR C WP9 D Internal data bus Reset SCI Input enable RP9 Serial receive data Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: n = 2, 3 Figure C.8 (c) Port 9 Block Diagram (Pin P92, P93) Rev.3.00 Mar. 26, 2007 Page 666 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Reset R Q D P9nDDR C WP9D Reset R P9n Q P9nDR C WP9 Clock output enable Clock output D Internal data bus SCI Clock input enable RP9 Clock input Interrupt controller IRQ4, IRQ5 input Legend: WP9D: Write to P9DDR WP9: Write to port 9 RP9: Read port 9 Note: n = 4 and 5 Figure C.8 (d) Port 9 Block Diagram (Pin P94, P95) Rev.3.00 Mar. 26, 2007 Page 667 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams C.9 Port A Block Diagram Reset R Q D PAnDDR C WPAD Reset R Internal data bus WPA TPC TPC output enable PAn Q PAnDR C D Next data Output trigger ITU RPA Counter input clock Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Note: n = 0 or 1 Figure C.9 (a) Port A Block Diagram (Pins PA0, PA1) Rev.3.00 Mar. 26, 2007 Page 668 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Reset R Q D PAnDDR C WPAD Reset R PAn Q PAnDR C WPA D Internal data bus TPC TPC output enable Next data Output trigger ITU Output enable Compare match output Input capture input Counter input clock RPA Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Note: n = 2 or 3 Figure C.9 (b) Port A Block Diagram (Pins PA2, PA3) Rev.3.00 Mar. 26, 2007 Page 669 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams R Q D PAnDDR C WPAD Reset R PAn Q PAnDR C WPA D Internal data bus Reset Internal address bus Software standby Address output enable Mode 3 TPC TPC output enable Next data Output trigger ITU Output enable Compare match output RPA Input capture input Legend: WPAD: Write to PADDR WPA: Write to port A RPA: Read port A Notes: n = 4 to 7 PA7 address output enable is fixed at 1 in mode 3. Figure C.9 (c) Port A Block Diagram (Pins PA4 to PA7) Rev.3.00 Mar. 26, 2007 Page 670 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams C.10 Port B Block Diagram Reset R Q D PBnDDR C WPBD Reset R Q D Next data Internal data bus TPC TPC output enable PBn PBnDR C WPB Output trigger ITU Output enable Compare match output RPB Input capture input Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Note: n = 0 to 3 Figure C.10 (a) Port B Block Diagram (Pins PB0 to PB3) Rev.3.00 Mar. 26, 2007 Page 671 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Reset R Q D PBnDDR C WPBD Reset R PBn Q PBnDR C WPB D Internal data bus TPC TPC output enable Next data Output trigger ITU Output enable Compare match output RPB Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Note: n = 4 or 5 Figure C.10 (b) Port B Block Diagram (Pins PB4, PB5) Rev.3.00 Mar. 26, 2007 Page 672 of 682 REJ09B0353-0300 Appendix C I/O Block Diagrams Reset R Q D PB7DDR C WPBD Reset R PB7 Q PB7DR C WPB D Internal data bus TPC TPC output enable Next data Output trigger A/D converter ADTRG input RPB Legend: WPBD: Write to PBDDR WPB: Write to port B RPB: Read port B Figure C.10 (c) Port B Block Diagram (Pin PB7) Rev.3.00 Mar. 26, 2007 Page 673 of 682 REJ09B0353-0300 Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Port States Mode -- 1 Table D.1 Pin Name RESO* Reset State Clock output T* L T 2 Hardware Standby Mode T T T T Software Standby Mode H T T keep T Program Execution State Sleep Mode Clock output RESO A7 to A0 Input port (DDR = 0) A7 to A0 (DDR = 1) I/O port A15 to A8 Input port (DDR = 0) A15 to A8 (DDR = 1) I/O port D7 to D0 I/O port A19 to A16 Input port (DDR = 0) A19 to A16 (DDR = 1) I/O port I/O port, WAIT I/O port WR, RD, AS I/O port Input port I/O port I/O port -- 1, 3 5 P17 to P10 6, 7 P27 to P20 1, 3 5 T L T T T T keep T keep T 6, 7 P37 to P30 P53 to P50 1, 3, 5 6, 7 1, 3 5 T T T L T T T T T T keep T keep T keep T 6, 7 P60 P65 to P63 P77 to P70 P80 1, 3, 5 6, 7 1, 3, 5 6, 7 1, 3, 5 to 7 1, 3, 5 6, 7 T T T H T T T T T T T T T T T T keep keep keep T keep T keep keep Rev.3.00 Mar. 26, 2007 Page 674 of 682 REJ09B0353-0300 Appendix D Pin States Reset State T Hardware Standby Mode T Software Standby Mode T [DDR = 0] H [DDR = 1] 6, 7 P95 to P90 PA 3 to PA 0 PA6 to PA4 1, 3, 5 to 7 1, 3, 5 to 7 3 T T T T T T T T keep keep keep [ADRCR = 0] T [ADRCR = 1] keep 1, 5, 6, 7 PA7 PB7, PB5 to PB0 Legend: H: L: T: keep: DDR: ADRCR: 3 1, 5, 6, 7 1, 3, 5 to 7 T L T T T T T T keep T keep keep Program Execution State Sleep Mode Input port [DDR = 0] H [DDR = 1] I/O port I/O port I/O port (ADRCR = 0) A21 to A23 (ADRCR = 1) I/O port I/O port A20 I/O port I/O port Pin Name P81 Mode 1, 3, 5 High Low High-impedance state Input pins are in the high-impedance state; output pins maintain their previous state. Data direction register bit Address control register Notes: 1 Mask ROM version. Dedicated FWE input pin for the F-ZTAT version. 2 Low output only when WDT overflows causes a reset. Rev.3.00 Mar. 26, 2007 Page 675 of 682 REJ09B0353-0300 Appendix D Pin States D.2 Pin States at Reset Reset in T1 State Figure D.1 is a timing diagram for the case in which RES goes low during the T1 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled. Sampling of RES takes place at the fall of the system clock (). Access to external address T1 T2 T3 RES Internal reset signal Address bus (modes 1, 3, 5) AS (modes 1, 3, 5) RD (read access) (modes 1, 3, 5) WR (write access) (modes 1, 3, 5) Data bus (write access) (modes 1, 3, 5) I/O port (modes 1, 3, 5 to 7) H'000000 High High High High impedance High impedance Figure D.1 Reset during Memory Access (Reset during T1 State) Rev.3.00 Mar. 26, 2007 Page 676 of 682 REJ09B0353-0300 Appendix D Pin States Reset in T2 State Figure D.2 is a timing diagram for the case in which RES goes low during the T2 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus is initialized to the low output level 0.5 state after the low level of RES is sampled. The same timing applies when a reset occurs during a wait state (TW). Access to external address T1 T2 T3 RES Internal reset signal Address bus (modes 1, 3, 5) AS (modes 1, 3, 5) RD (read access) (modes 1, 3, 5) WR (write access) (modes 1, 3, 5) Data bus (write access) (modes 1, 3, 5) I/O port (modes 1, 3, 5 to 7) High impedance H'000000 High impedance Figure D.2 Reset during Memory Access (Reset during T2 State) Rev.3.00 Mar. 26, 2007 Page 677 of 682 REJ09B0353-0300 Appendix D Pin States Reset in T3 State Figure D.3 is a timing diagram for the case in which RES goes low during the T3 state of an external memory access cycle. As soon as RES goes low, all ports are initialized to the input state. AS, RD, and WR go high, and the data bus goes to the high-impedance state. The address bus outputs are held during the T3 state.The same timing applies when a reset occurs in the T2 state of an access cycle to a two-state-access area. Access to external address T1 T2 T3 RES Internal reset signal Address bus (modes 1, 3, 5) AS (modes 1, 3, 5) RD (read access) (modes 1, 3, 5) WR (write access) (modes 1, 3, 5) Data bus (write access) (modes 1, 3, 5) I/O port (modes 1, 3, 5 to 7) High impedance H'000000 High impedance Figure D.3 Reset during Memory Access (Reset during T3 State) Rev.3.00 Mar. 26, 2007 Page 678 of 682 REJ09B0353-0300 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low 10 system clock cycles before the STBY signal goes low, as shown below. RES must remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns). STBY t1 10tcyc RES t2 0 ns (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low approximately 100 ns before STBY goes high. STBY t 100 ns RES tOSC Rev.3.00 Mar. 26, 2007 Page 679 of 682 REJ09B0353-0300 Appendix F Product Lineup Appendix F Product Lineup Table F.1 Product Type H8/3039 Flash memory version 5V version 3V version Mask ROM version 5V version 3V version H8/3038 Mask ROM version 5V version 3V version H8/3037 Mask ROM version 5V version 3V version H8/3036 Mask ROM version 5V version 3V version H8/3039 Group Product Lineup Part Number HD64F3039F HD64F3039TE HD64F3039VF HD64F3039VTE HD6433039F HD6433039TE HD6433039VF HD6433039VTE HD6433038F HD6433038TE HD6433038VF HD6433038VTE HD6433037F HD6433037TE HD6433037VF HD6433037VTE HD6433036F HD6433036TE HD6433036VF HD6433036VTE Mark Code HD64F3039F HD64F3039TE HD64F3039VF HD64F3039VTE HD6433039(***)F HD6433039(***)TE HD6433039(***)VF HD6433039(***)VTE HD6433038(***)F HD6433038(***)TE HD6433038(***)VF HD6433038(***)VTE HD6433037(***)F HD6433037(***)TE HD6433037(***)VF HD6433037(***)VTE HD6433036(***)F HD6433036(***)TE HD6433036(***)VF HD6433036(***)VTE Package (Package Code) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) 80-pin QFP (FP-80A) 80-pin TQFP (TFP-80C) Note: (***) in mask ROM versions is the ROM code. Rev.3.00 Mar. 26, 2007 Page 680 of 682 REJ09B0353-0300 Appendix G Package Dimensions Appendix G Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-QFP80-14x14-0.65 RENESAS Code PRQP0080JB-A Previous Code FP-80A/FP-80AV MASS[Typ.] 1.2g HD *1 D 60 41 61 40 bp b1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. c1 *2 HE E c Terminal cross section ZE Reference Dimension in Millimeters Symbol 80 21 1 ZD 20 A2 F A1 L L1 Detail F e *3 y bp x M D E A2 HD HE A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 14 14 2.70 16.9 17.2 17.5 16.9 17.2 17.5 3.05 0.00 0.10 0.25 0.24 0.32 0.40 0.30 0.12 0.17 0.22 0.15 0 8 0.65 0.12 0.10 0.83 0.83 0.5 0.8 1.1 1.6 Min Figure G.1 Package Dimensions (FP-80A) Rev.3.00 Mar. 26, 2007 Page 681 of 682 REJ09B0353-0300 A c Appendix G Package Dimensions JEITA Package Code P-TQFP80-12x12-0.50 RENESAS Code PTQP0080KC-A Previous Code TFP-80C/TFP-80CV MASS[Typ.] 0.4g HD *1 D 41 60 61 40 bp b1 c1 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. *2 HE E c Terminal cross section 80 21 ZE Reference Dimension in Millimeters Symbol 1 ZD Index mark 20 A2 F A1 L L1 e *3 y bp Detail F x M D E A2 HD H1 A A1 bp b1 c c1 e x y ZD ZE L L1 Nom Max 12 12 1.00 13.8 14.0 14.2 13.8 14.0 14.2 1.20 0.00 0.10 0.20 0.17 0.22 0.27 0.20 0.12 0.17 0.22 0.15 0 8 0.5 0.10 0.10 1.25 1.25 0.4 0.5 0.6 1.0 Min Figure G.2 Package Dimensions (TFP-80C) Rev.3.00 Mar. 26, 2007 Page 682 of 682 REJ09B0353-0300 A c Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3039 Group, H8/3039F-ZTATTM Publication Date: 1st Edition, December 1997 Rev.3.00, March 26, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2007. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145 http://www.renesas.com Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510 Colophon 6.0 H8/3039 Group, H8/3039F-ZTATTM Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan |
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